diff mbox series

[1/8] drm/i915/icl: create function to identify combophy port

Message ID 20181003072203.12848-2-mahesh1.kumar@intel.com (mailing list archive)
State New, archived
Headers show
Series Refactor and Add helper function for combophy/tc ports | expand

Commit Message

Kumar, Mahesh Oct. 3, 2018, 7:21 a.m. UTC 
This patch creates a function/wrapper to check if port is combophy port
instead of explicitly comparing ports.

Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
Cc: Madhav Chauhan <madhav.chauhan@intel.com>
Cc: Manasi Navare <manasi.d.navare@intel.com>
---
 drivers/gpu/drm/i915/intel_ddi.c     | 15 ++++++++-------
 drivers/gpu/drm/i915/intel_display.c | 11 +++++++++++
 drivers/gpu/drm/i915/intel_drv.h     |  1 +
 3 files changed, 20 insertions(+), 7 deletions(-)

Comments

Rodrigo Vivi Oct. 3, 2018, 5:57 p.m. UTC | #1 
On Wed, Oct 03, 2018 at 12:51:56PM +0530, Mahesh Kumar wrote:
> This patch creates a function/wrapper to check if port is combophy port
> instead of explicitly comparing ports.
> 
> Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
> Cc: Madhav Chauhan <madhav.chauhan@intel.com>
> Cc: Manasi Navare <manasi.d.navare@intel.com>

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> ---
>  drivers/gpu/drm/i915/intel_ddi.c     | 15 ++++++++-------
>  drivers/gpu/drm/i915/intel_display.c | 11 +++++++++++
>  drivers/gpu/drm/i915/intel_drv.h     |  1 +
>  3 files changed, 20 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index 7f34d3955ca1..b5b8dae06cde 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -916,7 +916,7 @@ static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port por
>  	level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
>  
>  	if (IS_ICELAKE(dev_priv)) {
> -		if (port == PORT_A || port == PORT_B)
> +		if (intel_port_is_combophy(dev_priv, port))
>  			icl_get_combo_buf_trans(dev_priv, port,
>  						INTEL_OUTPUT_HDMI, &n_entries);
>  		else
> @@ -1535,7 +1535,7 @@ static void icl_ddi_clock_get(struct intel_encoder *encoder,
>  	uint32_t pll_id;
>  
>  	pll_id = intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll);
> -	if (port == PORT_A || port == PORT_B) {
> +	if (intel_port_is_combophy(dev_priv, port)) {
>  		if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI))
>  			link_clock = cnl_calc_wrpll_link(dev_priv, pll_id);
>  		else
> @@ -2235,7 +2235,7 @@ u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder)
>  	int n_entries;
>  
>  	if (IS_ICELAKE(dev_priv)) {
> -		if (port == PORT_A || port == PORT_B)
> +		if (intel_port_is_combophy(dev_priv, port))
>  			icl_get_combo_buf_trans(dev_priv, port, encoder->type,
>  						&n_entries);
>  		else
> @@ -2669,9 +2669,10 @@ static void icl_ddi_vswing_sequence(struct intel_encoder *encoder,
>  				    u32 level,
>  				    enum intel_output_type type)
>  {
> +	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>  	enum port port = encoder->port;
>  
> -	if (port == PORT_A || port == PORT_B)
> +	if (intel_port_is_combophy(dev_priv, port))
>  		icl_combo_phy_ddi_vswing_sequence(encoder, level, type);
>  	else
>  		icl_mg_phy_ddi_vswing_sequence(encoder, link_clock, level);
> @@ -2757,7 +2758,7 @@ void icl_map_plls_to_ports(struct drm_crtc *crtc,
>  		val = I915_READ(DPCLKA_CFGCR0_ICL);
>  		WARN_ON((val & DPCLKA_CFGCR0_DDI_CLK_OFF(port)) == 0);
>  
> -		if (port == PORT_A || port == PORT_B) {
> +		if (intel_port_is_combophy(dev_priv, port)) {
>  			val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
>  			val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);
>  			I915_WRITE(DPCLKA_CFGCR0_ICL, val);
> @@ -2810,7 +2811,7 @@ static void intel_ddi_clk_select(struct intel_encoder *encoder,
>  	mutex_lock(&dev_priv->dpll_lock);
>  
>  	if (IS_ICELAKE(dev_priv)) {
> -		if (port >= PORT_C)
> +		if (!intel_port_is_combophy(dev_priv, port))
>  			I915_WRITE(DDI_CLK_SEL(port),
>  				   icl_pll_to_ddi_pll_sel(encoder, pll));
>  	} else if (IS_CANNONLAKE(dev_priv)) {
> @@ -2852,7 +2853,7 @@ static void intel_ddi_clk_disable(struct intel_encoder *encoder)
>  	enum port port = encoder->port;
>  
>  	if (IS_ICELAKE(dev_priv)) {
> -		if (port >= PORT_C)
> +		if (!intel_port_is_combophy(dev_priv, port))
>  			I915_WRITE(DDI_CLK_SEL(port), DDI_CLK_SEL_NONE);
>  	} else if (IS_CANNONLAKE(dev_priv)) {
>  		I915_WRITE(DPCLKA_CFGCR0, I915_READ(DPCLKA_CFGCR0) |
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 4c5c2b39e65c..916eb71e78ed 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5947,6 +5947,17 @@ enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, enum port port)
>  	return port - PORT_C;
>  }
>  
> +bool intel_port_is_combophy(struct drm_i915_private *dev_priv, enum port port)
> +{
> +	if (port == PORT_NONE)
> +		return false;
> +
> +	if (IS_ICELAKE(dev_priv))
> +		return (port <= PORT_B);
> +
> +	return false;
> +}
> +
>  enum intel_display_power_domain intel_port_to_power_domain(enum port port)
>  {
>  	switch (port) {
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index cbcae246d742..86567f26138b 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1443,6 +1443,7 @@ void icl_map_plls_to_ports(struct drm_crtc *crtc,
>  void icl_unmap_plls_to_ports(struct drm_crtc *crtc,
>  			     struct intel_crtc_state *crtc_state,
>  			     struct drm_atomic_state *old_state);
> +bool intel_port_is_combophy(struct drm_i915_private *dev_priv, enum port port);
>  
>  unsigned int intel_fb_align_height(const struct drm_framebuffer *fb,
>  				   int color_plane, unsigned int height);
> -- 
> 2.16.2
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Lucas De Marchi Oct. 3, 2018, 6:03 p.m. UTC | #2 
On Wed, Oct 03, 2018 at 12:51:56PM +0530, Mahesh Kumar wrote:
> This patch creates a function/wrapper to check if port is combophy port
> instead of explicitly comparing ports.
> 
> Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
> Cc: Madhav Chauhan <madhav.chauhan@intel.com>
> Cc: Manasi Navare <manasi.d.navare@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_ddi.c     | 15 ++++++++-------
>  drivers/gpu/drm/i915/intel_display.c | 11 +++++++++++
>  drivers/gpu/drm/i915/intel_drv.h     |  1 +
>  3 files changed, 20 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index 7f34d3955ca1..b5b8dae06cde 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -916,7 +916,7 @@ static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port por
>  	level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
>  
>  	if (IS_ICELAKE(dev_priv)) {
> -		if (port == PORT_A || port == PORT_B)
> +		if (intel_port_is_combophy(dev_priv, port))
>  			icl_get_combo_buf_trans(dev_priv, port,
>  						INTEL_OUTPUT_HDMI, &n_entries);
>  		else
> @@ -1535,7 +1535,7 @@ static void icl_ddi_clock_get(struct intel_encoder *encoder,
>  	uint32_t pll_id;
>  
>  	pll_id = intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll);
> -	if (port == PORT_A || port == PORT_B) {
> +	if (intel_port_is_combophy(dev_priv, port)) {
>  		if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI))
>  			link_clock = cnl_calc_wrpll_link(dev_priv, pll_id);
>  		else
> @@ -2235,7 +2235,7 @@ u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder)
>  	int n_entries;
>  
>  	if (IS_ICELAKE(dev_priv)) {
> -		if (port == PORT_A || port == PORT_B)
> +		if (intel_port_is_combophy(dev_priv, port))
>  			icl_get_combo_buf_trans(dev_priv, port, encoder->type,
>  						&n_entries);
>  		else
> @@ -2669,9 +2669,10 @@ static void icl_ddi_vswing_sequence(struct intel_encoder *encoder,
>  				    u32 level,
>  				    enum intel_output_type type)
>  {
> +	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>  	enum port port = encoder->port;
>  
> -	if (port == PORT_A || port == PORT_B)
> +	if (intel_port_is_combophy(dev_priv, port))
>  		icl_combo_phy_ddi_vswing_sequence(encoder, level, type);
>  	else
>  		icl_mg_phy_ddi_vswing_sequence(encoder, link_clock, level);
> @@ -2757,7 +2758,7 @@ void icl_map_plls_to_ports(struct drm_crtc *crtc,
>  		val = I915_READ(DPCLKA_CFGCR0_ICL);
>  		WARN_ON((val & DPCLKA_CFGCR0_DDI_CLK_OFF(port)) == 0);
>  
> -		if (port == PORT_A || port == PORT_B) {
> +		if (intel_port_is_combophy(dev_priv, port)) {
>  			val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
>  			val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);
>  			I915_WRITE(DPCLKA_CFGCR0_ICL, val);
> @@ -2810,7 +2811,7 @@ static void intel_ddi_clk_select(struct intel_encoder *encoder,
>  	mutex_lock(&dev_priv->dpll_lock);
>  
>  	if (IS_ICELAKE(dev_priv)) {
> -		if (port >= PORT_C)
> +		if (!intel_port_is_combophy(dev_priv, port))
>  			I915_WRITE(DDI_CLK_SEL(port),
>  				   icl_pll_to_ddi_pll_sel(encoder, pll));
>  	} else if (IS_CANNONLAKE(dev_priv)) {
> @@ -2852,7 +2853,7 @@ static void intel_ddi_clk_disable(struct intel_encoder *encoder)
>  	enum port port = encoder->port;
>  
>  	if (IS_ICELAKE(dev_priv)) {
> -		if (port >= PORT_C)
> +		if (!intel_port_is_combophy(dev_priv, port))
>  			I915_WRITE(DDI_CLK_SEL(port), DDI_CLK_SEL_NONE);
>  	} else if (IS_CANNONLAKE(dev_priv)) {
>  		I915_WRITE(DPCLKA_CFGCR0, I915_READ(DPCLKA_CFGCR0) |
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 4c5c2b39e65c..916eb71e78ed 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5947,6 +5947,17 @@ enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, enum port port)
>  	return port - PORT_C;
>  }
>  
> +bool intel_port_is_combophy(struct drm_i915_private *dev_priv, enum port port)
> +{
> +	if (port == PORT_NONE)
> +		return false;
> +
> +	if (IS_ICELAKE(dev_priv))
> +		return (port <= PORT_B);

please remove parenthesis

> +
> +	return false;
> +}
> +
>  enum intel_display_power_domain intel_port_to_power_domain(enum port port)
>  {
>  	switch (port) {
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index cbcae246d742..86567f26138b 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1443,6 +1443,7 @@ void icl_map_plls_to_ports(struct drm_crtc *crtc,
>  void icl_unmap_plls_to_ports(struct drm_crtc *crtc,
>  			     struct intel_crtc_state *crtc_state,
>  			     struct drm_atomic_state *old_state);
> +bool intel_port_is_combophy(struct drm_i915_private *dev_priv, enum port port);

this should be together with the other helper with the same namespace, i.e. on top
of intel_port_is_tc()

Lucas De Marchi

>  
>  unsigned int intel_fb_align_height(const struct drm_framebuffer *fb,
>  				   int color_plane, unsigned int height);
> -- 
> 2.16.2
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Navare, Manasi Oct. 15, 2018, 9:58 p.m. UTC | #3 
On Wed, Oct 03, 2018 at 12:51:56PM +0530, Mahesh Kumar wrote:
> This patch creates a function/wrapper to check if port is combophy port
> instead of explicitly comparing ports.
> 
> Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
> Cc: Madhav Chauhan <madhav.chauhan@intel.com>
> Cc: Manasi Navare <manasi.d.navare@intel.com>

Looks good to me.

Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>

Manasi

> ---
>  drivers/gpu/drm/i915/intel_ddi.c     | 15 ++++++++-------
>  drivers/gpu/drm/i915/intel_display.c | 11 +++++++++++
>  drivers/gpu/drm/i915/intel_drv.h     |  1 +
>  3 files changed, 20 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index 7f34d3955ca1..b5b8dae06cde 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -916,7 +916,7 @@ static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port por
>  	level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
>  
>  	if (IS_ICELAKE(dev_priv)) {
> -		if (port == PORT_A || port == PORT_B)
> +		if (intel_port_is_combophy(dev_priv, port))
>  			icl_get_combo_buf_trans(dev_priv, port,
>  						INTEL_OUTPUT_HDMI, &n_entries);
>  		else
> @@ -1535,7 +1535,7 @@ static void icl_ddi_clock_get(struct intel_encoder *encoder,
>  	uint32_t pll_id;
>  
>  	pll_id = intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll);
> -	if (port == PORT_A || port == PORT_B) {
> +	if (intel_port_is_combophy(dev_priv, port)) {
>  		if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI))
>  			link_clock = cnl_calc_wrpll_link(dev_priv, pll_id);
>  		else
> @@ -2235,7 +2235,7 @@ u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder)
>  	int n_entries;
>  
>  	if (IS_ICELAKE(dev_priv)) {
> -		if (port == PORT_A || port == PORT_B)
> +		if (intel_port_is_combophy(dev_priv, port))
>  			icl_get_combo_buf_trans(dev_priv, port, encoder->type,
>  						&n_entries);
>  		else
> @@ -2669,9 +2669,10 @@ static void icl_ddi_vswing_sequence(struct intel_encoder *encoder,
>  				    u32 level,
>  				    enum intel_output_type type)
>  {
> +	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>  	enum port port = encoder->port;
>  
> -	if (port == PORT_A || port == PORT_B)
> +	if (intel_port_is_combophy(dev_priv, port))
>  		icl_combo_phy_ddi_vswing_sequence(encoder, level, type);
>  	else
>  		icl_mg_phy_ddi_vswing_sequence(encoder, link_clock, level);
> @@ -2757,7 +2758,7 @@ void icl_map_plls_to_ports(struct drm_crtc *crtc,
>  		val = I915_READ(DPCLKA_CFGCR0_ICL);
>  		WARN_ON((val & DPCLKA_CFGCR0_DDI_CLK_OFF(port)) == 0);
>  
> -		if (port == PORT_A || port == PORT_B) {
> +		if (intel_port_is_combophy(dev_priv, port)) {
>  			val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
>  			val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);
>  			I915_WRITE(DPCLKA_CFGCR0_ICL, val);
> @@ -2810,7 +2811,7 @@ static void intel_ddi_clk_select(struct intel_encoder *encoder,
>  	mutex_lock(&dev_priv->dpll_lock);
>  
>  	if (IS_ICELAKE(dev_priv)) {
> -		if (port >= PORT_C)
> +		if (!intel_port_is_combophy(dev_priv, port))
>  			I915_WRITE(DDI_CLK_SEL(port),
>  				   icl_pll_to_ddi_pll_sel(encoder, pll));
>  	} else if (IS_CANNONLAKE(dev_priv)) {
> @@ -2852,7 +2853,7 @@ static void intel_ddi_clk_disable(struct intel_encoder *encoder)
>  	enum port port = encoder->port;
>  
>  	if (IS_ICELAKE(dev_priv)) {
> -		if (port >= PORT_C)
> +		if (!intel_port_is_combophy(dev_priv, port))
>  			I915_WRITE(DDI_CLK_SEL(port), DDI_CLK_SEL_NONE);
>  	} else if (IS_CANNONLAKE(dev_priv)) {
>  		I915_WRITE(DPCLKA_CFGCR0, I915_READ(DPCLKA_CFGCR0) |
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 4c5c2b39e65c..916eb71e78ed 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5947,6 +5947,17 @@ enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, enum port port)
>  	return port - PORT_C;
>  }
>  
> +bool intel_port_is_combophy(struct drm_i915_private *dev_priv, enum port port)
> +{
> +	if (port == PORT_NONE)
> +		return false;
> +
> +	if (IS_ICELAKE(dev_priv))
> +		return (port <= PORT_B);
> +
> +	return false;
> +}
> +
>  enum intel_display_power_domain intel_port_to_power_domain(enum port port)
>  {
>  	switch (port) {
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index cbcae246d742..86567f26138b 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1443,6 +1443,7 @@ void icl_map_plls_to_ports(struct drm_crtc *crtc,
>  void icl_unmap_plls_to_ports(struct drm_crtc *crtc,
>  			     struct intel_crtc_state *crtc_state,
>  			     struct drm_atomic_state *old_state);
> +bool intel_port_is_combophy(struct drm_i915_private *dev_priv, enum port port);
>  
>  unsigned int intel_fb_align_height(const struct drm_framebuffer *fb,
>  				   int color_plane, unsigned int height);
> -- 
> 2.16.2
>
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 7f34d3955ca1..b5b8dae06cde 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -916,7 +916,7 @@  static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port por
 	level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
 
 	if (IS_ICELAKE(dev_priv)) {
-		if (port == PORT_A || port == PORT_B)
+		if (intel_port_is_combophy(dev_priv, port))
 			icl_get_combo_buf_trans(dev_priv, port,
 						INTEL_OUTPUT_HDMI, &n_entries);
 		else
@@ -1535,7 +1535,7 @@  static void icl_ddi_clock_get(struct intel_encoder *encoder,
 	uint32_t pll_id;
 
 	pll_id = intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll);
-	if (port == PORT_A || port == PORT_B) {
+	if (intel_port_is_combophy(dev_priv, port)) {
 		if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI))
 			link_clock = cnl_calc_wrpll_link(dev_priv, pll_id);
 		else
@@ -2235,7 +2235,7 @@  u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder)
 	int n_entries;
 
 	if (IS_ICELAKE(dev_priv)) {
-		if (port == PORT_A || port == PORT_B)
+		if (intel_port_is_combophy(dev_priv, port))
 			icl_get_combo_buf_trans(dev_priv, port, encoder->type,
 						&n_entries);
 		else
@@ -2669,9 +2669,10 @@  static void icl_ddi_vswing_sequence(struct intel_encoder *encoder,
 				    u32 level,
 				    enum intel_output_type type)
 {
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	enum port port = encoder->port;
 
-	if (port == PORT_A || port == PORT_B)
+	if (intel_port_is_combophy(dev_priv, port))
 		icl_combo_phy_ddi_vswing_sequence(encoder, level, type);
 	else
 		icl_mg_phy_ddi_vswing_sequence(encoder, link_clock, level);
@@ -2757,7 +2758,7 @@  void icl_map_plls_to_ports(struct drm_crtc *crtc,
 		val = I915_READ(DPCLKA_CFGCR0_ICL);
 		WARN_ON((val & DPCLKA_CFGCR0_DDI_CLK_OFF(port)) == 0);
 
-		if (port == PORT_A || port == PORT_B) {
+		if (intel_port_is_combophy(dev_priv, port)) {
 			val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
 			val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);
 			I915_WRITE(DPCLKA_CFGCR0_ICL, val);
@@ -2810,7 +2811,7 @@  static void intel_ddi_clk_select(struct intel_encoder *encoder,
 	mutex_lock(&dev_priv->dpll_lock);
 
 	if (IS_ICELAKE(dev_priv)) {
-		if (port >= PORT_C)
+		if (!intel_port_is_combophy(dev_priv, port))
 			I915_WRITE(DDI_CLK_SEL(port),
 				   icl_pll_to_ddi_pll_sel(encoder, pll));
 	} else if (IS_CANNONLAKE(dev_priv)) {
@@ -2852,7 +2853,7 @@  static void intel_ddi_clk_disable(struct intel_encoder *encoder)
 	enum port port = encoder->port;
 
 	if (IS_ICELAKE(dev_priv)) {
-		if (port >= PORT_C)
+		if (!intel_port_is_combophy(dev_priv, port))
 			I915_WRITE(DDI_CLK_SEL(port), DDI_CLK_SEL_NONE);
 	} else if (IS_CANNONLAKE(dev_priv)) {
 		I915_WRITE(DPCLKA_CFGCR0, I915_READ(DPCLKA_CFGCR0) |
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 4c5c2b39e65c..916eb71e78ed 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5947,6 +5947,17 @@  enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, enum port port)
 	return port - PORT_C;
 }
 
+bool intel_port_is_combophy(struct drm_i915_private *dev_priv, enum port port)
+{
+	if (port == PORT_NONE)
+		return false;
+
+	if (IS_ICELAKE(dev_priv))
+		return (port <= PORT_B);
+
+	return false;
+}
+
 enum intel_display_power_domain intel_port_to_power_domain(enum port port)
 {
 	switch (port) {
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index cbcae246d742..86567f26138b 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1443,6 +1443,7 @@  void icl_map_plls_to_ports(struct drm_crtc *crtc,
 void icl_unmap_plls_to_ports(struct drm_crtc *crtc,
 			     struct intel_crtc_state *crtc_state,
 			     struct drm_atomic_state *old_state);
+bool intel_port_is_combophy(struct drm_i915_private *dev_priv, enum port port);
 
 unsigned int intel_fb_align_height(const struct drm_framebuffer *fb,
 				   int color_plane, unsigned int height);