| Message ID | 20181016220133.26991-10-paulo.r.zanoni@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | More watermarks improvements | expand |
On Tue, Oct 16, 2018 at 03:01:31PM -0700, Paulo Zanoni wrote: > The function only really needs dev_priv to make its decision. If we > ever need more, we can change it again. But then, in this case we > should make needs_memory_bw_wa be a variable inside struct > skl_wm_params so we won't need to keep passing intel states deep > inside pure watermark value calculation functions. Again, I tend to disagree with the notion that wm_params is somehow better than the atomic state(s) proper. But the patch itself looks fine so Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > > Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> > --- > drivers/gpu/drm/i915/intel_pm.c | 14 ++++---------- > 1 file changed, 4 insertions(+), 10 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index 1290efc64869..d101c542f10d 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -3599,10 +3599,8 @@ static u8 intel_enabled_dbuf_slices_num(struct drm_i915_private *dev_priv) > * FIXME: We still don't have the proper code detect if we need to apply the WA, > * so assume we'll always need it in order to avoid underruns. > */ > -static bool skl_needs_memory_bw_wa(struct intel_atomic_state *state) > +static bool skl_needs_memory_bw_wa(const struct drm_i915_private *dev_priv) > { > - struct drm_i915_private *dev_priv = to_i915(state->base.dev); > - > if (IS_GEN9_BC(dev_priv) || IS_BROXTON(dev_priv)) > return true; > > @@ -3765,7 +3763,7 @@ bool intel_can_enable_sagv(struct drm_atomic_state *state) > > latency = dev_priv->wm.skl_latency[level]; > > - if (skl_needs_memory_bw_wa(intel_state) && > + if (skl_needs_memory_bw_wa(dev_priv) && > plane->base.state->fb->modifier == > I915_FORMAT_MOD_X_TILED) > latency += 15; > @@ -4530,9 +4528,7 @@ skl_compute_plane_wm_params(const struct drm_i915_private *dev_priv, > const struct drm_framebuffer *fb = pstate->fb; > enum pipe pipe = to_intel_crtc(cstate->base.crtc)->pipe; > uint32_t interm_pbpl; > - struct intel_atomic_state *state = > - to_intel_atomic_state(cstate->base.state); > - bool apply_memory_bw_wa = skl_needs_memory_bw_wa(state); > + bool apply_memory_bw_wa = skl_needs_memory_bw_wa(dev_priv); > > wp->plane_visible = intel_wm_plane_visible(cstate, intel_pstate); > if (!wp->plane_visible) > @@ -4644,9 +4640,7 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv, > uint_fixed_16_16_t method1, method2; > uint_fixed_16_16_t selected_result; > uint32_t res_blocks, res_lines; > - struct intel_atomic_state *state = > - to_intel_atomic_state(cstate->base.state); > - bool apply_memory_bw_wa = skl_needs_memory_bw_wa(state); > + bool apply_memory_bw_wa = skl_needs_memory_bw_wa(dev_priv); > uint32_t min_disp_buf_needed; > > if (latency == 0) { > -- > 2.14.4 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 1290efc64869..d101c542f10d 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -3599,10 +3599,8 @@ static u8 intel_enabled_dbuf_slices_num(struct drm_i915_private *dev_priv) * FIXME: We still don't have the proper code detect if we need to apply the WA, * so assume we'll always need it in order to avoid underruns. */ -static bool skl_needs_memory_bw_wa(struct intel_atomic_state *state) +static bool skl_needs_memory_bw_wa(const struct drm_i915_private *dev_priv) { - struct drm_i915_private *dev_priv = to_i915(state->base.dev); - if (IS_GEN9_BC(dev_priv) || IS_BROXTON(dev_priv)) return true; @@ -3765,7 +3763,7 @@ bool intel_can_enable_sagv(struct drm_atomic_state *state) latency = dev_priv->wm.skl_latency[level]; - if (skl_needs_memory_bw_wa(intel_state) && + if (skl_needs_memory_bw_wa(dev_priv) && plane->base.state->fb->modifier == I915_FORMAT_MOD_X_TILED) latency += 15; @@ -4530,9 +4528,7 @@ skl_compute_plane_wm_params(const struct drm_i915_private *dev_priv, const struct drm_framebuffer *fb = pstate->fb; enum pipe pipe = to_intel_crtc(cstate->base.crtc)->pipe; uint32_t interm_pbpl; - struct intel_atomic_state *state = - to_intel_atomic_state(cstate->base.state); - bool apply_memory_bw_wa = skl_needs_memory_bw_wa(state); + bool apply_memory_bw_wa = skl_needs_memory_bw_wa(dev_priv); wp->plane_visible = intel_wm_plane_visible(cstate, intel_pstate); if (!wp->plane_visible) @@ -4644,9 +4640,7 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv, uint_fixed_16_16_t method1, method2; uint_fixed_16_16_t selected_result; uint32_t res_blocks, res_lines; - struct intel_atomic_state *state = - to_intel_atomic_state(cstate->base.state); - bool apply_memory_bw_wa = skl_needs_memory_bw_wa(state); + bool apply_memory_bw_wa = skl_needs_memory_bw_wa(dev_priv); uint32_t min_disp_buf_needed; if (latency == 0) {
The function only really needs dev_priv to make its decision. If we ever need more, we can change it again. But then, in this case we should make needs_memory_bw_wa be a variable inside struct skl_wm_params so we won't need to keep passing intel states deep inside pure watermark value calculation functions. Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> --- drivers/gpu/drm/i915/intel_pm.c | 14 ++++---------- 1 file changed, 4 insertions(+), 10 deletions(-)