From patchwork Tue Oct 16 22:01:31 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Zanoni, Paulo R" X-Patchwork-Id: 10644253 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 3F80B181D for ; Tue, 16 Oct 2018 22:01:47 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 311902AA03 for ; Tue, 16 Oct 2018 22:01:47 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 254E42AA09; Tue, 16 Oct 2018 22:01:47 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id D16132AA03 for ; Tue, 16 Oct 2018 22:01:46 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 6FAD26E2B6; Tue, 16 Oct 2018 22:01:39 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by gabe.freedesktop.org (Postfix) with ESMTPS id 58E1D6E2A9 for ; Tue, 16 Oct 2018 22:01:37 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga104.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 16 Oct 2018 15:01:36 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.54,389,1534834800"; d="scan'208";a="100014523" Received: from przanoni-mobl.jf.intel.com ([10.24.8.134]) by orsmga001.jf.intel.com with ESMTP; 16 Oct 2018 15:01:35 -0700 From: Paulo Zanoni To: intel-gfx@lists.freedesktop.org Date: Tue, 16 Oct 2018 15:01:31 -0700 Message-Id: <20181016220133.26991-10-paulo.r.zanoni@intel.com> X-Mailer: git-send-email 2.14.4 In-Reply-To: <20181016220133.26991-1-paulo.r.zanoni@intel.com> References: <20181016220133.26991-1-paulo.r.zanoni@intel.com> Subject: [Intel-gfx] [PATCH 09/11] drm/i915: make skl_needs_memory_bw_wa() take dev_priv instead of state X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paulo Zanoni MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP The function only really needs dev_priv to make its decision. If we ever need more, we can change it again. But then, in this case we should make needs_memory_bw_wa be a variable inside struct skl_wm_params so we won't need to keep passing intel states deep inside pure watermark value calculation functions. Signed-off-by: Paulo Zanoni Reviewed-by: Ville Syrjälä --- drivers/gpu/drm/i915/intel_pm.c | 14 ++++---------- 1 file changed, 4 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 1290efc64869..d101c542f10d 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -3599,10 +3599,8 @@ static u8 intel_enabled_dbuf_slices_num(struct drm_i915_private *dev_priv) * FIXME: We still don't have the proper code detect if we need to apply the WA, * so assume we'll always need it in order to avoid underruns. */ -static bool skl_needs_memory_bw_wa(struct intel_atomic_state *state) +static bool skl_needs_memory_bw_wa(const struct drm_i915_private *dev_priv) { - struct drm_i915_private *dev_priv = to_i915(state->base.dev); - if (IS_GEN9_BC(dev_priv) || IS_BROXTON(dev_priv)) return true; @@ -3765,7 +3763,7 @@ bool intel_can_enable_sagv(struct drm_atomic_state *state) latency = dev_priv->wm.skl_latency[level]; - if (skl_needs_memory_bw_wa(intel_state) && + if (skl_needs_memory_bw_wa(dev_priv) && plane->base.state->fb->modifier == I915_FORMAT_MOD_X_TILED) latency += 15; @@ -4530,9 +4528,7 @@ skl_compute_plane_wm_params(const struct drm_i915_private *dev_priv, const struct drm_framebuffer *fb = pstate->fb; enum pipe pipe = to_intel_crtc(cstate->base.crtc)->pipe; uint32_t interm_pbpl; - struct intel_atomic_state *state = - to_intel_atomic_state(cstate->base.state); - bool apply_memory_bw_wa = skl_needs_memory_bw_wa(state); + bool apply_memory_bw_wa = skl_needs_memory_bw_wa(dev_priv); wp->plane_visible = intel_wm_plane_visible(cstate, intel_pstate); if (!wp->plane_visible) @@ -4644,9 +4640,7 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv, uint_fixed_16_16_t method1, method2; uint_fixed_16_16_t selected_result; uint32_t res_blocks, res_lines; - struct intel_atomic_state *state = - to_intel_atomic_state(cstate->base.state); - bool apply_memory_bw_wa = skl_needs_memory_bw_wa(state); + bool apply_memory_bw_wa = skl_needs_memory_bw_wa(dev_priv); uint32_t min_disp_buf_needed; if (latency == 0) {