From patchwork Tue Oct 16 22:01:25 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Zanoni, Paulo R" X-Patchwork-Id: 10644255 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 8FAE613AD for ; Tue, 16 Oct 2018 22:01:48 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 7FF512AA03 for ; Tue, 16 Oct 2018 22:01:48 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 718E92AA09; Tue, 16 Oct 2018 22:01:48 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 12CF32AA03 for ; Tue, 16 Oct 2018 22:01:48 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id E439D6E2BB; Tue, 16 Oct 2018 22:01:39 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by gabe.freedesktop.org (Postfix) with ESMTPS id A2F626E297 for ; Tue, 16 Oct 2018 22:01:36 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga104.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 16 Oct 2018 15:01:36 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.54,389,1534834800"; d="scan'208";a="100014503" Received: from przanoni-mobl.jf.intel.com ([10.24.8.134]) by orsmga001.jf.intel.com with ESMTP; 16 Oct 2018 15:01:35 -0700 From: Paulo Zanoni To: intel-gfx@lists.freedesktop.org Date: Tue, 16 Oct 2018 15:01:25 -0700 Message-Id: <20181016220133.26991-4-paulo.r.zanoni@intel.com> X-Mailer: git-send-email 2.14.4 In-Reply-To: <20181016220133.26991-1-paulo.r.zanoni@intel.com> References: <20181016220133.26991-1-paulo.r.zanoni@intel.com> Subject: [Intel-gfx] [PATCH 03/11] drm/i915: fix handling of invisible planes in watermarks code X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paulo Zanoni MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Before the patch, if a plane was not visible, skl_compute_plane_wm_params() would return early without writing anything to the wm_params struct. This would leave garbage in the struct since it is not previously zeroed, and then we would later check for wm_params.is_planar, which could be true due to the usage of uninitialized memory. This would lead us to calculate the zeroed watermarks for the second inexistent plane and mark the plane as a planar plane. Then later this check would affect our decisions in skl_write_plane_wm(). I can't see how this would lead to a noticeable bug in our code, but it leads us to calculate watermarks for every level + transition watermarks, twice (due to the is_planar bug). So the fix saves us a lot of instructions. This problem was found when I decided to add a DRM_ERROR for the currently unsupported planar formats on ICL: kms_cursor_legacy would trigger the error message without using planar formats. So the fix we adopt in this patch is to create a new watermark parameter called plane_visible and use it to avoid computing the watermarks for invisible planes later. We also remove the checks that are now made redundant by it. Testcase: igt/kms_cursor_legacy/nonblocking-modeset-vs-cursor-atomic Signed-off-by: Paulo Zanoni Reviewed-by: Ville Syrjälä --- drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/intel_pm.c | 15 ++++++--------- 2 files changed, 7 insertions(+), 9 deletions(-) The error message mentioned above isd the one added by patch 06 of the series. diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 3616b718b5d2..4b1e8471609b 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1250,6 +1250,7 @@ struct skl_wm_level { /* Stores plane specific WM parameters */ struct skl_wm_params { + bool plane_visible; bool x_tiled, y_tiled; bool rc_surface; bool is_planar; diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 18157c6ee126..9043ffe40ce8 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -4532,7 +4532,8 @@ skl_compute_plane_wm_params(const struct drm_i915_private *dev_priv, to_intel_atomic_state(cstate->base.state); bool apply_memory_bw_wa = skl_needs_memory_bw_wa(state); - if (!intel_wm_plane_visible(cstate, intel_pstate)) + wp->plane_visible = intel_wm_plane_visible(cstate, intel_pstate); + if (!wp->plane_visible) return 0; /* only NV12 format has two planes */ @@ -4645,8 +4646,7 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv, bool apply_memory_bw_wa = skl_needs_memory_bw_wa(state); uint32_t min_disp_buf_needed; - if (latency == 0 || - !intel_wm_plane_visible(cstate, intel_pstate)) { + if (latency == 0) { result->plane_en = false; return 0; } @@ -4805,9 +4805,6 @@ skl_compute_wm_levels(const struct drm_i915_private *dev_priv, enum plane_id intel_plane_id = intel_plane->id; int ret; - if (WARN_ON(!intel_pstate->base.fb)) - return -EINVAL; - ddb_blocks = plane_id ? skl_ddb_entry_size(&ddb->uv_plane[pipe][intel_plane_id]) : skl_ddb_entry_size(&ddb->plane[pipe][intel_plane_id]); @@ -4876,9 +4873,6 @@ static void skl_compute_transition_wm(struct intel_crtc_state *cstate, const uint16_t trans_amount = 10; /* This is configurable amount */ uint16_t wm0_sel_res_b, trans_offset_b, res_blocks; - if (!cstate->base.active) - goto exit; - /* Transition WM are not recommended by HW team for GEN9 */ if (INTEL_GEN(dev_priv) <= 9) goto exit; @@ -4965,6 +4959,9 @@ static int skl_build_pipe_wm(struct intel_crtc_state *cstate, if (ret) return ret; + if (!wm_params.plane_visible) + continue; + ret = skl_compute_wm_levels(dev_priv, ddb, cstate, intel_pstate, &wm_params, wm, 0); if (ret)