From patchwork Thu Oct 18 15:28:09 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tvrtko Ursulin X-Patchwork-Id: 10647505 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 9A1F6112B for ; Thu, 18 Oct 2018 15:28:45 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 3609128C20 for ; Thu, 18 Oct 2018 15:28:45 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 2841D28D0A; Thu, 18 Oct 2018 15:28:45 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 649AE28C20 for ; Thu, 18 Oct 2018 15:28:44 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 812AA6E09B; Thu, 18 Oct 2018 15:28:41 +0000 (UTC) X-Original-To: Intel-gfx@lists.freedesktop.org Delivered-To: Intel-gfx@lists.freedesktop.org Received: from mail-wr1-x442.google.com (mail-wr1-x442.google.com [IPv6:2a00:1450:4864:20::442]) by gabe.freedesktop.org (Postfix) with ESMTPS id 622336E01C for ; Thu, 18 Oct 2018 15:28:35 +0000 (UTC) Received: by mail-wr1-x442.google.com with SMTP id w5-v6so34158775wrt.2 for ; Thu, 18 Oct 2018 08:28:35 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=p6kejeN9GmUjQ3uXGEBOBtol18l2LPcsGg90G6zLK4g=; b=gD+DoLhWFOWdxFVgG5vvxjOGkFH4Vj4b9yPEEHk9f1lGcl4oxa5mp8FY/39QsPQzhL rGSbCu3MJnDLeVkMq4I4eFkoOau/nhgHmoUyK/M1Y8QgNvWR7ENZooCmtboVKI0q3Yjo yLEA8WS9V4Rpp/wl8snWCx/7alDVH/jkTv8PH200lMeRXXi4hMkFDWIO3aqnFD3tgls4 IsMfnwAHW+iiqhyTZFp7LYyu9OiZ98dCKMAOs9VURAh2TONCEUGObj5WhhLJukA9FKBT H8R6IhjwPZ74/zWwZm75dzSlPfk17bWt13mKP2zY3q5e2oA65W4ySljro+qFmEHTKXqg Qu4w== X-Gm-Message-State: AGRZ1gIlgjCFktQZeUpz8oOmXQ58Fo8Ddg6YUnRXcDLP/ubyEu4K3vxm RoOLgBAt/sbQiYBVfwZ/idkK2g== X-Google-Smtp-Source: AJdET5e9+mj+Xq4q8yC+2QSnNE6QENKhpbgsHdFIct+MhPonSO2Y2DyEbFxY+KwOeA0/PaAklTP8sA== X-Received: by 2002:adf:dc89:: with SMTP id r9-v6mr3130326wrj.212.1539876513570; Thu, 18 Oct 2018 08:28:33 -0700 (PDT) Received: from localhost.localdomain ([91.110.193.16]) by smtp.gmail.com with ESMTPSA id i6-v6sm19530387wrq.4.2018.10.18.08.28.32 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 18 Oct 2018 08:28:32 -0700 (PDT) From: Tvrtko Ursulin X-Google-Original-From: Tvrtko Ursulin To: igt-dev@lists.freedesktop.org Date: Thu, 18 Oct 2018 16:28:09 +0100 Message-Id: <20181018152815.31816-12-tvrtko.ursulin@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181018152815.31816-1-tvrtko.ursulin@linux.intel.com> References: <20181018152815.31816-1-tvrtko.ursulin@linux.intel.com> Subject: [Intel-gfx] [PATCH i-g-t 11/17] gem_wsim: Engine map support X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Intel-gfx@lists.freedesktop.org MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP From: Tvrtko Ursulin Support new i915 uAPI for configuring contexts with engine maps. Please refer to the README file for more detailed explanation. Signed-off-by: Tvrtko Ursulin --- benchmarks/gem_wsim.c | 212 ++++++++++++++++++++++++++++++++++------- benchmarks/wsim/README | 17 +++- 2 files changed, 192 insertions(+), 37 deletions(-) diff --git a/benchmarks/gem_wsim.c b/benchmarks/gem_wsim.c index 17325d2ceaf6..fbec23ad1753 100644 --- a/benchmarks/gem_wsim.c +++ b/benchmarks/gem_wsim.c @@ -56,6 +56,7 @@ #include "ewma.h" enum intel_engine_id { + DEFAULT, RCS, BCS, VCS, @@ -80,7 +81,8 @@ enum w_type SW_FENCE, SW_FENCE_SIGNAL, CTX_PRIORITY, - PREEMPTION + PREEMPTION, + ENGINE_MAP }; struct deps @@ -114,6 +116,10 @@ struct w_step int throttle; int fence_signal; int priority; + struct { + unsigned int engine_map_count; + enum intel_engine_id *engine_map; + }; }; /* Implementation details */ @@ -143,6 +149,8 @@ DECLARE_EWMA(uint64_t, rt, 4, 2) struct ctx { uint32_t id; int priority; + unsigned int engine_map_count; + enum intel_engine_id *engine_map; bool targets_instance; bool wants_balance; unsigned int static_vcs; @@ -201,10 +209,10 @@ struct workload int fd; bool first; unsigned int num_engines; - unsigned int engine_map[5]; + unsigned int engine_map[NUM_ENGINES]; uint64_t t_prev; - uint64_t prev[5]; - double busy[5]; + uint64_t prev[NUM_ENGINES]; + double busy[NUM_ENGINES]; } busy_balancer; }; @@ -235,6 +243,7 @@ static int fd; #define REG(x) (volatile uint32_t *)((volatile char *)igt_global_mmio + x) static const char *ring_str_map[NUM_ENGINES] = { + [DEFAULT] = "DEFAULT", [RCS] = "RCS", [BCS] = "BCS", [VCS] = "VCS", @@ -331,6 +340,37 @@ static int str_to_engine(const char *str) return -1; } +static int parse_engine_map(struct w_step *step, const char *_str) +{ + char *token, *tctx = NULL, *tstart = (char *)_str; + + while ((token = strtok_r(tstart, "|", &tctx))) { + enum intel_engine_id engine; + + tstart = NULL; + + if (!strcmp(token, "DEFAULT")) + return -1; + else if (!strcmp(token, "VCS")) + return -1; + + engine = str_to_engine(token); + if ((int)engine < 0) + return -1; + + if (engine != VCS1 && engine != VCS2) + return -1; /* TODO */ + + step->engine_map_count++; + step->engine_map = realloc(step->engine_map, + step->engine_map_count * + sizeof(step->engine_map[0])); + step->engine_map[step->engine_map_count - 1] = engine; + } + + return 0; +} + static struct workload * parse_workload(struct w_arg *arg, unsigned int flags, struct workload *app_w) { @@ -449,6 +489,33 @@ parse_workload(struct w_arg *arg, unsigned int flags, struct workload *app_w) } else if (!strcmp(field, "f")) { step.type = SW_FENCE; goto add_step; + } else if (!strcmp(field, "M")) { + unsigned int nr = 0; + while ((field = strtok_r(fstart, ".", &fctx)) != + NULL) { + tmp = atoi(field); + check_arg(nr == 0 && tmp <= 0, + "Invalid context at step %u!\n", + nr_steps); + check_arg(nr > 1, + "Invalid engine map format at step %u!\n", + nr_steps); + + if (nr == 0) { + step.context = tmp; + } else { + tmp = parse_engine_map(&step, + field); + check_arg(tmp < 0, + "Invalid engine map list at step %u!\n", + nr_steps); + } + + nr++; + } + + step.type = ENGINE_MAP; + goto add_step; } else if (!strcmp(field, "X")) { unsigned int nr = 0; while ((field = strtok_r(fstart, ".", &fctx)) != @@ -490,9 +557,7 @@ parse_workload(struct w_arg *arg, unsigned int flags, struct workload *app_w) i = str_to_engine(field); check_arg(i < 0, "Invalid engine id at step %u!\n", nr_steps); - if (i >= 0) - valid++; - + valid++; step.engine = i; if (step.engine == BCS) @@ -769,6 +834,7 @@ terminate_bb(struct w_step *w, unsigned int flags) } static const unsigned int eb_engine_map[NUM_ENGINES] = { + [DEFAULT] = I915_EXEC_DEFAULT, [RCS] = I915_EXEC_RENDER, [BCS] = I915_EXEC_BLT, [VCS] = I915_EXEC_BSD, @@ -785,18 +851,42 @@ eb_set_engine(struct drm_i915_gem_execbuffer2 *eb, if (engine == VCS2 && (flags & VCS2REMAP)) engine = BCS; - if ((flags & I915) && engine == VCS) { + if ((flags & I915) && engine == VCS) eb->flags = 0; - } else { + else eb->flags = eb_engine_map[engine]; +} + +static unsigned int +find_engine_in_map(struct ctx *ctx, enum intel_engine_id engine) +{ + unsigned int i; + + for (i = 0; i < ctx->engine_map_count; i++) { + if (ctx->engine_map[i] == engine) + return i + 1; } + + igt_assert(0); + return 0; +} + +static struct ctx * +__get_ctx(struct workload *wrk, struct w_step *w) +{ + return &wrk->ctx_list[w->context * 2]; } static void -eb_update_flags(struct w_step *w, enum intel_engine_id engine, - unsigned int flags) +eb_update_flags(struct workload *wrk, struct w_step *w, + enum intel_engine_id engine, unsigned int flags) { - eb_set_engine(&w->eb, engine, flags); + struct ctx *ctx = __get_ctx(wrk, w); + + if (ctx->engine_map) + w->eb.flags = find_engine_in_map(ctx, engine); + else + eb_set_engine(&w->eb, engine, flags); w->eb.flags |= I915_EXEC_HANDLE_LUT; w->eb.flags |= I915_EXEC_NO_RELOC; @@ -815,12 +905,6 @@ get_status_objects(struct workload *wrk) return wrk->status_object; } -static struct ctx * -__get_ctx(struct workload *wrk, struct w_step *w) -{ - return &wrk->ctx_list[w->context * 2]; -} - static uint32_t get_ctxid(struct workload *wrk, struct w_step *w) { @@ -890,7 +974,7 @@ alloc_step_batch(struct workload *wrk, struct w_step *w, unsigned int flags) engine = VCS2; else if (flags & SWAPVCS && engine == VCS2) engine = VCS1; - eb_update_flags(w, engine, flags); + eb_update_flags(wrk, w, engine, flags); #ifdef DEBUG printf("%u: %u:|", w->idx, w->eb.buffer_count); for (i = 0; i <= j; i++) @@ -913,7 +997,7 @@ static void __ctx_set_prio(uint32_t ctx_id, unsigned int prio) gem_context_set_param(fd, ¶m); } -static void +static int prepare_workload(unsigned int id, struct workload *wrk, unsigned int flags) { unsigned int ctx_vcs = 0; @@ -974,30 +1058,53 @@ prepare_workload(unsigned int id, struct workload *wrk, unsigned int flags) /* * Identify if contexts target specific engine instances and if they * want to be balanced. + * + * Transfer over engine map configuration from the workload step. */ for (j = 0; j < wrk->nr_ctxs; j += 2) { bool targets = false; bool balance = false; for (i = 0, w = wrk->steps; i < wrk->nr_steps; i++, w++) { - if (w->type != BATCH) - continue; - if (w->context != (j / 2)) continue; - if (w->engine == VCS) - balance = true; - else - targets = true; + if (w->type == BATCH) { + if (w->engine == VCS) + balance = true; + else + targets = true; + } else if (w->type == ENGINE_MAP) { + wrk->ctx_list[j].engine_map = w->engine_map; + wrk->ctx_list[j].engine_map_count = + w->engine_map_count; + } } - if (flags & I915) { - wrk->ctx_list[j].targets_instance = targets; + wrk->ctx_list[j].targets_instance = targets; + if (flags & I915) wrk->ctx_list[j].wants_balance = balance; + } + + /* + * Ensure VCS is not allowed with engine map contexts. + */ + for (j = 0; j < wrk->nr_ctxs; j += 2) { + for (i = 0, w = wrk->steps; i < wrk->nr_steps; i++, w++) { + if (w->context != (j / 2)) + continue; + + if (w->type != BATCH) + continue; + + if (wrk->ctx_list[j].engine_map && w->engine == VCS) { + wsim_err("Batches targetting engine maps must use explicit engines!\n"); + return -1; + } } } + /* * Create and configure contexts. */ @@ -1008,7 +1115,7 @@ prepare_workload(unsigned int id, struct workload *wrk, unsigned int flags) if (ctx->id) continue; - if (flags & I915) { + if ((flags & I915) || ctx->engine_map) { struct drm_i915_gem_context_create_v2 args = { }; /* Find existing context to share ppgtt with. */ @@ -1022,7 +1129,7 @@ prepare_workload(unsigned int id, struct workload *wrk, unsigned int flags) break; } - if (!ctx->targets_instance) + if ((!ctx->engine_map && !ctx->targets_instance)) args.flags |= I915_GEM_CONTEXT_SINGLE_TIMELINE; drmIoctl(fd, DRM_IOCTL_I915_GEM_CONTEXT_CREATE, &args); @@ -1053,7 +1160,7 @@ prepare_workload(unsigned int id, struct workload *wrk, unsigned int flags) * both want to target specific engines and be balanced by i915? */ if ((flags & I915) && ctx->wants_balance && - ctx->targets_instance) { + ctx->targets_instance && !ctx->engine_map) { struct drm_i915_gem_context_create_v2 args = {}; igt_assert(share_ctx); @@ -1071,7 +1178,33 @@ prepare_workload(unsigned int id, struct workload *wrk, unsigned int flags) __ctx_set_prio(ctx_id, wrk->prio); } - if (ctx->wants_balance) { + if (ctx->engine_map) { + struct local_i915_context_param_engines { + __u64 extensions; + + struct { + __u16 class; /* see enum drm_i915_gem_engine_class */ + __u16 instance; + } engines[ctx->engine_map_count]; + } __attribute__((packed)) set_engines; + struct drm_i915_gem_context_param param = { + .ctx_id = ctx_id, + .param = I915_CONTEXT_PARAM_ENGINES, + .size = sizeof(set_engines), + .value = to_user_pointer(&set_engines), + }; + + set_engines.extensions = 0; + + for (j = 0; j < ctx->engine_map_count; j++) { + set_engines.engines[j].class = + I915_ENGINE_CLASS_VIDEO; /* FIXME */ + set_engines.engines[j].instance = + ctx->engine_map[j] - VCS1; /* FIXME */ + } + + gem_context_set_param(fd, ¶m); + } else if (ctx->wants_balance) { struct i915_context_engines_load_balance load_balance = { .base.name = I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE, .engines_mask = -1, @@ -1151,6 +1284,8 @@ prepare_workload(unsigned int id, struct workload *wrk, unsigned int flags) alloc_step_batch(wrk, w, _flags); } + + return 0; } static double elapsed(const struct timespec *start, const struct timespec *end) @@ -1888,7 +2023,7 @@ do_eb(struct workload *wrk, struct w_step *w, enum intel_engine_id engine, uint32_t seqno = new_seqno(wrk, engine); unsigned int i; - eb_update_flags(w, engine, flags); + eb_update_flags(wrk, w, engine, flags); if (flags & SEQNO) update_bb_seqno(w, engine, seqno); @@ -2037,7 +2172,8 @@ static void *run_workload(void *data) w->priority; } continue; - } else if (w->type == PREEMPTION) { + } else if (w->type == PREEMPTION || + w->type == ENGINE_MAP) { continue; } @@ -2595,7 +2731,11 @@ int main(int argc, char **argv) w[i]->print_stats = verbose > 1 || (verbose > 0 && master_workload == i); - prepare_workload(i, w[i], flags_); + if (prepare_workload(i, w[i], flags_)) { + wsim_err("Failed to prepare workload %u!\n", i); + return 1; + } + if (balancer && balancer->init) { int ret = balancer->init(balancer, w[i]); diff --git a/benchmarks/wsim/README b/benchmarks/wsim/README index 4786f116b4ac..20e3e358cd2e 100644 --- a/benchmarks/wsim/README +++ b/benchmarks/wsim/README @@ -3,6 +3,7 @@ Workload descriptor format ctx.engine.duration_us.dependency.wait,... ..[-].[/][...].<0|1>,... +M..[|]... P|X.. d|p|s|t|q|a.,... f @@ -23,10 +24,11 @@ Additional workload steps are also supported: 'q' - Throttle to n max queue depth. 'f' - Create a sync fence. 'a' - Advance the previously created sync fence. + 'M' - Set up engine map. 'P' - Context priority. 'X' - Context preemption control. -Engine ids: RCS, BCS, VCS, VCS1, VCS2, VECS +Engine ids: DEFAULT, RCS, BCS, VCS, VCS1, VCS2, VECS Example (leading spaces must not be present in the actual file): ---------------------------------------------------------------- @@ -161,3 +163,16 @@ The same context is then marked to have batches which can be preempted every Same as with context priority, context preemption commands are valid until optionally overriden by another preemption control change on the same context. + +Engine maps +----------- + +Engine maps are a per context feature which changes the way engine selection is +done in the driver. + +Example: + + 1.M.VCS1|VCS2 + +This sets up context 1 with an engine map containing VCS1 and VCS2 engine. +Submission to this context can now only reference these two engines.