From patchwork Thu Oct 18 15:28:12 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tvrtko Ursulin X-Patchwork-Id: 10647521 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id AC14115E2 for ; Thu, 18 Oct 2018 15:29:11 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 9C85E28C76 for ; Thu, 18 Oct 2018 15:29:11 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 8F67128D6A; Thu, 18 Oct 2018 15:29:11 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 71C4628D9D for ; Thu, 18 Oct 2018 15:29:10 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 056FF6E0C4; Thu, 18 Oct 2018 15:28:49 +0000 (UTC) X-Original-To: Intel-gfx@lists.freedesktop.org Delivered-To: Intel-gfx@lists.freedesktop.org Received: from mail-wm1-x341.google.com (mail-wm1-x341.google.com [IPv6:2a00:1450:4864:20::341]) by gabe.freedesktop.org (Postfix) with ESMTPS id 0DD756E046 for ; Thu, 18 Oct 2018 15:28:38 +0000 (UTC) Received: by mail-wm1-x341.google.com with SMTP id z25-v6so2106596wmf.1 for ; Thu, 18 Oct 2018 08:28:37 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=gfeeCR0ktdW4ZiIsms24sfxaB4glyLIcPBU2i4H3DjQ=; b=uJGDQc8AqC/EuGh90pUBGHJxZZecXoK8xPwjY1fENEuSVc5Emz4ND6n1FvNbxDxU57 Bpni0ZTZyTkL9HrOHm3oxjR9KCXb/F04iA3nPm3noMCtujDX56+c6kQ5eSHrb4OUVkUv o9ySL1Fnn5DVB1fxT/Rs2nQU1U2RRCTAEBGWnNKginx9DqA4pisUxE3zCOYfTRg7NZnA I/Hb4+XqeCQuv2KC/83HCe28tmYKLvw5fixT/SY+OJhHvFiNPFVR9TQjsrkHVcRWCGY9 CfZFYBYms2MIz3quPF9VoCrw4PTM7rj6Pg74dm8m2CDLHjjydA7oRUTDxdK20uWF6N0o 5MZA== X-Gm-Message-State: AGRZ1gLKzGsIhSi7ch8gJJmkiTpitHk3+zCWYryPQhra+80WxLBt7Eqq dBcdJcyxfvcq/71BgPeZCVtCEg== X-Google-Smtp-Source: ACcGV61725/B3yizuS7lzEJPmvH6MKY5sezocu6wSjLOjya5p9iXWZ4S+R0z3i50VqoLCGBzLf8qlg== X-Received: by 2002:a1c:3c4:: with SMTP id 187-v6mr813120wmd.90.1539876516317; Thu, 18 Oct 2018 08:28:36 -0700 (PDT) Received: from localhost.localdomain ([91.110.193.16]) by smtp.gmail.com with ESMTPSA id i6-v6sm19530387wrq.4.2018.10.18.08.28.35 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 18 Oct 2018 08:28:35 -0700 (PDT) From: Tvrtko Ursulin X-Google-Original-From: Tvrtko Ursulin To: igt-dev@lists.freedesktop.org Date: Thu, 18 Oct 2018 16:28:12 +0100 Message-Id: <20181018152815.31816-15-tvrtko.ursulin@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181018152815.31816-1-tvrtko.ursulin@linux.intel.com> References: <20181018152815.31816-1-tvrtko.ursulin@linux.intel.com> Subject: [Intel-gfx] [PATCH i-g-t 14/17] gem_wsim: Engine map load balance command X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Intel-gfx@lists.freedesktop.org MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP From: Tvrtko Ursulin A new workload command for enabling a load balanced context map (aka Virtual Engine). Example usage: 1.B This turns on load balancing for context one, assuming it has already been configured with an engine map. Only DEFAULT engine specifier can be used with load balanced engine maps. Signed-off-by: Tvrtko Ursulin --- benchmarks/gem_wsim.c | 62 +++++++++++++++++++++++++++++++++++++----- benchmarks/wsim/README | 18 ++++++++++++ 2 files changed, 73 insertions(+), 7 deletions(-) diff --git a/benchmarks/gem_wsim.c b/benchmarks/gem_wsim.c index b805ecd9a680..a772e2c588b5 100644 --- a/benchmarks/gem_wsim.c +++ b/benchmarks/gem_wsim.c @@ -82,7 +82,8 @@ enum w_type SW_FENCE_SIGNAL, CTX_PRIORITY, PREEMPTION, - ENGINE_MAP + ENGINE_MAP, + LOAD_BALANCE, }; struct deps @@ -120,6 +121,7 @@ struct w_step unsigned int engine_map_count; enum intel_engine_id *engine_map; }; + bool load_balance; }; /* Implementation details */ @@ -502,6 +504,25 @@ parse_workload(struct w_arg *arg, unsigned int flags, struct workload *app_w) step.type = PREEMPTION; goto add_step; + } else if (!strcmp(field, "B")) { + unsigned int nr = 0; + while ((field = strtok_r(fstart, ".", &fctx))) { + tmp = atoi(field); + check_arg(nr == 0 && tmp <= 0, + "Invalid context at step %u!\n", + nr_steps); + check_arg(nr > 0, + "Invalid load balance format at step %u!\n", + nr_steps); + + step.context = tmp; + step.load_balance = true; + + nr++; + } + + step.type = LOAD_BALANCE; + goto add_step; } tmp = atoi(field); @@ -828,7 +849,7 @@ find_engine_in_map(struct ctx *ctx, enum intel_engine_id engine) return i + 1; } - igt_assert(0); + igt_assert(ctx->wants_balance); return 0; } @@ -1039,12 +1060,19 @@ prepare_workload(unsigned int id, struct workload *wrk, unsigned int flags) wrk->ctx_list[j].engine_map = w->engine_map; wrk->ctx_list[j].engine_map_count = w->engine_map_count; + } else if (w->type == LOAD_BALANCE) { + if (!wrk->ctx_list[j].engine_map) { + wsim_err("Load balancing needs an engine map!\n"); + return 1; + } + wrk->ctx_list[j].wants_balance = + w->load_balance; } } wrk->ctx_list[j].targets_instance = targets; if (flags & I915) - wrk->ctx_list[j].wants_balance = balance; + wrk->ctx_list[j].wants_balance |= balance; } /* @@ -1058,10 +1086,19 @@ prepare_workload(unsigned int id, struct workload *wrk, unsigned int flags) if (w->type != BATCH) continue; - if (wrk->ctx_list[j].engine_map && w->engine == VCS) { + if (wrk->ctx_list[j].engine_map && + !wrk->ctx_list[j].wants_balance && + (w->engine == VCS || w->engine == DEFAULT)) { wsim_err("Batches targetting engine maps must use explicit engines!\n"); return -1; } + + if (wrk->ctx_list[j].engine_map && + wrk->ctx_list[j].wants_balance && + w->engine != DEFAULT) { + wsim_err("Batches targetting load balanced maps must not use explicit engines!\n"); + return -1; + } } } @@ -1090,7 +1127,8 @@ prepare_workload(unsigned int id, struct workload *wrk, unsigned int flags) break; } - if ((!ctx->engine_map && !ctx->targets_instance)) + if ((!ctx->engine_map && !ctx->targets_instance) || + (ctx->engine_map && ctx->wants_balance)) args.flags |= I915_GEM_CONTEXT_SINGLE_TIMELINE; drmIoctl(fd, DRM_IOCTL_I915_GEM_CONTEXT_CREATE, &args); @@ -1154,8 +1192,17 @@ prepare_workload(unsigned int id, struct workload *wrk, unsigned int flags) .size = sizeof(set_engines), .value = to_user_pointer(&set_engines), }; + struct i915_context_engines_load_balance load_balance = + { .base.name = I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE, + .engines_mask = -1, + }; - set_engines.extensions = 0; + if (ctx->wants_balance) { + set_engines.extensions = + to_user_pointer(&load_balance); + } else { + set_engines.extensions = 0; + } for (j = 0; j < ctx->engine_map_count; j++) { set_engines.engines[j].class = @@ -2134,7 +2181,8 @@ static void *run_workload(void *data) } continue; } else if (w->type == PREEMPTION || - w->type == ENGINE_MAP) { + w->type == ENGINE_MAP || + w->type == LOAD_BALANCE) { continue; } diff --git a/benchmarks/wsim/README b/benchmarks/wsim/README index 20e3e358cd2e..58dada675357 100644 --- a/benchmarks/wsim/README +++ b/benchmarks/wsim/README @@ -3,6 +3,7 @@ Workload descriptor format ctx.engine.duration_us.dependency.wait,... ..[-].[/][...].<0|1>,... +B. M..[|]... P|X.. d|p|s|t|q|a.,... @@ -24,6 +25,7 @@ Additional workload steps are also supported: 'q' - Throttle to n max queue depth. 'f' - Create a sync fence. 'a' - Advance the previously created sync fence. + 'B' - Turn on context load balancing. 'M' - Set up engine map. 'P' - Context priority. 'X' - Context preemption control. @@ -176,3 +178,19 @@ Example: This sets up context 1 with an engine map containing VCS1 and VCS2 engine. Submission to this context can now only reference these two engines. + +Context load balancing +---------------------- + +Context load balancing (aka Virtual Engine) is an i915 feature where the driver +will pick the best engine (most idle) to submit to given previously configured +engine map. + +Example: + + 1.B + +This enables load balancing for context number one. + +Submissions to load balanced contexts are only allowed to use the DEFAULT engine +specifier.