From patchwork Tue Oct 30 00:34:10 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rodrigo Vivi X-Patchwork-Id: 10660411 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 0A80F1734 for ; Tue, 30 Oct 2018 00:34:33 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 0627F28726 for ; Tue, 30 Oct 2018 00:34:33 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id EE37129BA9; Tue, 30 Oct 2018 00:34:32 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 89D6F29C11 for ; Tue, 30 Oct 2018 00:34:32 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 5F2236E146; Tue, 30 Oct 2018 00:34:29 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by gabe.freedesktop.org (Postfix) with ESMTPS id 2A5F36E13D for ; Tue, 30 Oct 2018 00:34:24 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga106.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 29 Oct 2018 17:34:23 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.54,442,1534834800"; d="scan'208";a="245414658" Received: from rdvivi-vienna.jf.intel.com ([10.7.196.65]) by orsmga004.jf.intel.com with ESMTP; 29 Oct 2018 17:34:23 -0700 From: Rodrigo Vivi To: intel-gfx@lists.freedesktop.org Date: Mon, 29 Oct 2018 17:34:10 -0700 Message-Id: <20181030003413.8144-1-rodrigo.vivi@intel.com> X-Mailer: git-send-email 2.19.1 MIME-Version: 1.0 Subject: [Intel-gfx] [RFC 1/4] drm/i915: Add Display Gen info. X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jani Nikula , Lucas De Marchi , Rodrigo Vivi Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Introduce Display Gen. The goal is to use this to minimize the amount of platform codename checks we have nowdays on display code. The introduction of a new platform should be just gen >= current. Just a gen++ without exposing any new feature or ip. so this would minimize the amount of patches needed for a bring-up specially holding them on internal branches. Cc: Jani Nikula Cc: Lucas De Marchi Signed-off-by: Rodrigo Vivi --- drivers/gpu/drm/i915/i915_drv.h | 28 ++++++++++++++++++++++-- drivers/gpu/drm/i915/i915_pci.c | 5 ++++- drivers/gpu/drm/i915/intel_device_info.h | 2 ++ 3 files changed, 32 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index c9e5bab6861b..3242229688e3 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -2349,8 +2349,9 @@ intel_info(const struct drm_i915_private *dev_priv) #define INTEL_INFO(dev_priv) intel_info((dev_priv)) #define DRIVER_CAPS(dev_priv) (&(dev_priv)->caps) -#define INTEL_GEN(dev_priv) ((dev_priv)->info.gen) -#define INTEL_DEVID(dev_priv) ((dev_priv)->info.device_id) +#define INTEL_GEN(dev_priv) ((dev_priv)->info.gen) +#define INTEL_DISPLAY_GEN(dev_priv) ((dev_priv)->info.display_gen) +#define INTEL_DEVID(dev_priv) ((dev_priv)->info.device_id) #define REVID_FOREVER 0xff #define INTEL_REVID(dev_priv) ((dev_priv)->drm.pdev->revision) @@ -2363,6 +2364,8 @@ intel_info(const struct drm_i915_private *dev_priv) /* Returns true if Gen is in inclusive range [Start, End] */ #define IS_GEN(dev_priv, s, e) \ (!!((dev_priv)->info.gen_mask & INTEL_GEN_MASK((s), (e)))) +#define IS_DISPLAY_GEN(dev_priv, s, e) \ + (!!((dev_priv)->info.display_gen_mask & INTEL_GEN_MASK((s), (e)))) /* * Return true if revision is in range [since,until] inclusive. @@ -2532,6 +2535,27 @@ intel_info(const struct drm_i915_private *dev_priv) #define IS_GEN10(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(9))) #define IS_GEN11(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(10))) +#define IS_DISPLAY_GEN2(dev_priv) (!!((dev_priv)->info.display_gen_mask \ + & BIT(2))) +#define IS_DISPLAY_GEN3(dev_priv) (!!((dev_priv)->info.display_gen_mask \ + & BIT(3))) +#define IS_DISPLAY_GEN4(dev_priv) (!!((dev_priv)->info.display_gen_mask \ + & BIT(4))) +#define IS_DISPLAY_GEN5(dev_priv) (!!((dev_priv)->info.display_gen_mask \ + & BIT(5))) +#define IS_DISPLAY_GEN6(dev_priv) (!!((dev_priv)->info.display_gen_mask \ + & BIT(6))) +#define IS_DISPLAY_GEN7(dev_priv) (!!((dev_priv)->info.display_gen_mask \ + & BIT(7))) +#define IS_DISPLAY_GEN8(dev_priv) (!!((dev_priv)->info.display_gen_mask \ + & BIT(8))) +#define IS_DISPLAY_GEN9(dev_priv) (!!((dev_priv)->info.display_gen_mask \ + & BIT(9))) +#define IS_DISPLAY_GEN10(dev_priv) (!!((dev_priv)->info.display_gen_mask \ + & BIT(10))) +#define IS_DISPLAY_GEN11(dev_priv) (!!((dev_priv)->info.display_gen_mask \ + & BIT(11))) + #define IS_LP(dev_priv) (INTEL_INFO(dev_priv)->is_lp) #define IS_GEN9_LP(dev_priv) (IS_GEN9(dev_priv) && IS_LP(dev_priv)) #define IS_GEN9_BC(dev_priv) (IS_GEN9(dev_priv) && !IS_LP(dev_priv)) diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c index 44e745921ac1..fb8caf846c02 100644 --- a/drivers/gpu/drm/i915/i915_pci.c +++ b/drivers/gpu/drm/i915/i915_pci.c @@ -30,7 +30,10 @@ #include "i915_selftest.h" #define PLATFORM(x) .platform = (x), .platform_mask = BIT(x) -#define GEN(x) .gen = (x), .gen_mask = BIT((x) - 1) +#define GEN(x) .gen = (x), .gen_mask = BIT((x) - 1), \ + .display_gen = (x), .display_gen_mask = BIT((x)) +/* Unless explicitly stated otherwise Display gen inherits platform gen */ +#define DISPLAY_GEN(x) .display_gen = (x), .display_gen_mask = BIT((x)) #define GEN_DEFAULT_PIPEOFFSETS \ .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \ diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h index b4c2c4eae78b..9f31f29186a8 100644 --- a/drivers/gpu/drm/i915/intel_device_info.h +++ b/drivers/gpu/drm/i915/intel_device_info.h @@ -151,8 +151,10 @@ typedef u8 intel_ring_mask_t; struct intel_device_info { u16 device_id; u16 gen_mask; + u16 display_gen_mask; u8 gen; + u8 display_gen; u8 gt; /* GT number, 0 if undefined */ u8 num_rings; intel_ring_mask_t ring_mask; /* Rings supported by the HW */