From patchwork Thu Feb 14 02:57:10 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Santa, Carlos" X-Patchwork-Id: 10811641 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 41130922 for ; Thu, 14 Feb 2019 02:57:47 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 2DEB42DB83 for ; Thu, 14 Feb 2019 02:57:47 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 21FAE2DB9C; Thu, 14 Feb 2019 02:57:47 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 88E972DB83 for ; Thu, 14 Feb 2019 02:57:46 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id D3A966E849; Thu, 14 Feb 2019 02:57:44 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by gabe.freedesktop.org (Postfix) with ESMTPS id 0DA786E846 for ; Thu, 14 Feb 2019 02:57:44 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga105.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 13 Feb 2019 18:57:43 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.58,367,1544515200"; d="scan'208";a="124345905" Received: from miryad.jf.intel.com ([10.54.74.35]) by fmsmga008.fm.intel.com with ESMTP; 13 Feb 2019 18:57:43 -0800 From: Carlos Santa To: intel-gfx@lists.freedesktop.org Date: Wed, 13 Feb 2019 18:57:10 -0800 Message-Id: <20190214025713.34150-4-carlos.santa@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190214025713.34150-1-carlos.santa@intel.com> References: <20190214025713.34150-1-carlos.santa@intel.com> Subject: [Intel-gfx] [PATCH v3 3/6] drm/i915: Watchdog timeout: Ringbuffer command emission for gen8+ X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Michel Thierry MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP From: Michel Thierry Emit the required commands into the ring buffer for starting and stopping the watchdog timer before/after batch buffer start during batch buffer submission. v2: Support watchdog threshold per context engine, merge lri commands, and move watchdog commands emission to emit_bb_start. Request space of combined start_watchdog, bb_start and stop_watchdog to avoid any error after emitting bb_start. v3: There were too many req->engine in emit_bb_start. Use GEM_BUG_ON instead of returning a very late EINVAL in the remote case of watchdog misprogramming; set correct LRI cmd size in emit_stop_watchdog. (Chris) v4: Rebase. v5: use to_intel_context instead of ctx->engine. v6: Rebase. v7: Rebase, Store gpu watchdog capability in engine flag (Tvrtko) Store WATCHDOG_DISABLE magic # in engine (Tvrtko) No need to declare emit_{start|stop}_watchdog as vfuncs (Tvrtko) Replace flag watchdog_running with enable_watchdog (Tvrtko) Emit a single MI_NOOP by conditionally checking whether the # of emitted OPs is odd (Tvrtko) Cc: Chris Wilson Cc: Antonio Argenziano Cc: Tvrtko Ursulin Signed-off-by: Michel Thierry Signed-off-by: Carlos Santa --- drivers/gpu/drm/i915/i915_gem_context.h | 4 ++ drivers/gpu/drm/i915/intel_engine_cs.c | 2 + drivers/gpu/drm/i915/intel_lrc.c | 78 +++++++++++++++++++++++-- drivers/gpu/drm/i915/intel_lrc.h | 2 + drivers/gpu/drm/i915/intel_ringbuffer.h | 18 ++++-- 5 files changed, 96 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem_context.h b/drivers/gpu/drm/i915/i915_gem_context.h index b1eeac64da8b..dcf4e98666a6 100644 --- a/drivers/gpu/drm/i915/i915_gem_context.h +++ b/drivers/gpu/drm/i915/i915_gem_context.h @@ -183,6 +183,10 @@ struct i915_gem_context { u32 *lrc_reg_state; u64 lrc_desc; int pin_count; + /** watchdog_threshold: hw watchdog threshold value, + * in clock counts + */ + u32 watchdog_threshold; /** * active_tracker: Active tracker for the external rq activity diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c index 74f563d23cc8..438bf93a4340 100644 --- a/drivers/gpu/drm/i915/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/intel_engine_cs.c @@ -324,6 +324,8 @@ intel_engine_setup(struct drm_i915_private *dev_priv, if (engine->context_size) DRIVER_CAPS(dev_priv)->has_logical_contexts = true; + engine->watchdog_disable_id = get_watchdog_disable(engine); + /* Nothing to do here, execute in order of dependencies */ engine->schedule = NULL; diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index 41697fb468e3..abbac267c6f5 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -2193,16 +2193,74 @@ static void execlists_reset_finish(struct intel_engine_cs *engine) atomic_read(&execlists->tasklet.count)); } +static u32 *gen8_emit_start_watchdog(struct i915_request *rq, u32 *cs) +{ + struct intel_engine_cs *engine = rq->engine; + struct i915_gem_context *ctx = rq->gem_context; + struct intel_context *ce = to_intel_context(ctx, engine); + + GEM_BUG_ON(!intel_engine_supports_watchdog(engine)); + + /* + * watchdog register must never be programmed to zero. This would + * cause the watchdog counter to exceed and not allow the engine to + * go into IDLE state + */ + GEM_BUG_ON(ce->watchdog_threshold == 0); + + /* Set counter period */ + *cs++ = MI_LOAD_REGISTER_IMM(2); + *cs++ = i915_mmio_reg_offset(RING_THRESH(engine->mmio_base)); + *cs++ = ce->watchdog_threshold; + /* Start counter */ + *cs++ = i915_mmio_reg_offset(RING_CNTR(engine->mmio_base)); + *cs++ = GEN8_WATCHDOG_ENABLE; + + return cs; +} + +static u32 *gen8_emit_stop_watchdog(struct i915_request *rq, u32 *cs) +{ + struct intel_engine_cs *engine = rq->engine; + + GEM_BUG_ON(!intel_engine_supports_watchdog(engine)); + + *cs++ = MI_LOAD_REGISTER_IMM(1); + *cs++ = i915_mmio_reg_offset(RING_CNTR(engine->mmio_base)); + *cs++ = engine->watchdog_disable_id; + + return cs; +} + static int gen8_emit_bb_start(struct i915_request *rq, u64 offset, u32 len, const unsigned int flags) { + struct intel_engine_cs *engine = rq->engine; u32 *cs; + u32 num_dwords; + bool enable_watchdog = false; - cs = intel_ring_begin(rq, 6); + /* bb_start only */ + num_dwords = 6; + + /* check if watchdog will be required */ + if (to_intel_context(rq->gem_context, engine)->watchdog_threshold != 0) { + + /* + start_watchdog (6) + stop_watchdog (4) */ + num_dwords += 10; + enable_watchdog = true; + } + + cs = intel_ring_begin(rq, num_dwords); if (IS_ERR(cs)) return PTR_ERR(cs); + if (enable_watchdog) { + /* Start watchdog timer */ + cs = gen8_emit_start_watchdog(rq, cs); + } + /* * WaDisableCtxRestoreArbitration:bdw,chv * @@ -2229,10 +2287,16 @@ static int gen8_emit_bb_start(struct i915_request *rq, *cs++ = upper_32_bits(offset); *cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE; - *cs++ = MI_NOOP; - intel_ring_advance(rq, cs); + if (enable_watchdog) { + /* Cancel watchdog timer */ + cs = gen8_emit_stop_watchdog(rq, cs); + } + + if (*cs%2 != 0) + *cs++ = MI_NOOP; + intel_ring_advance(rq, cs); return 0; } @@ -2353,7 +2417,7 @@ static int gen8_emit_flush_render(struct i915_request *request, } /* From GEN9 onwards, all engines use the same RING_CNTR format */ -static inline u32 get_watchdog_disable(struct intel_engine_cs *engine) +u32 get_watchdog_disable(struct intel_engine_cs *engine) { if (engine->id == RCS || INTEL_GEN(engine->i915) >= 9) return GEN8_WATCHDOG_DISABLE; @@ -2548,6 +2612,9 @@ void intel_execlists_set_default_submission(struct intel_engine_cs *engine) I915_SCHEDULER_CAP_PRIORITY; if (intel_engine_has_preemption(engine)) engine->i915->caps.scheduler |= I915_SCHEDULER_CAP_PREEMPTION; + + if(engine->id != BCS) + engine->flags |= I915_ENGINE_SUPPORTS_WATCHDOG; } static void @@ -2726,6 +2793,9 @@ int logical_xcs_ring_init(struct intel_engine_cs *engine) if (err) return err; + /* BCS engine does not have a watchdog-expired irq */ + GEM_BUG_ON(!intel_engine_supports_watchdog(engine)); + return logical_ring_init(engine); } diff --git a/drivers/gpu/drm/i915/intel_lrc.h b/drivers/gpu/drm/i915/intel_lrc.h index 5779e776cc3f..9db4f6369574 100644 --- a/drivers/gpu/drm/i915/intel_lrc.h +++ b/drivers/gpu/drm/i915/intel_lrc.h @@ -120,4 +120,6 @@ void intel_virtual_engine_put(struct intel_engine_cs *engine); u32 gen8_make_rpcs(struct drm_i915_private *i915, struct intel_sseu *ctx_sseu); +u32 get_watchdog_disable(struct intel_engine_cs *engine); + #endif /* _INTEL_LRC_H_ */ diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h index 9c0c1d68f3a1..d5db04069e91 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.h +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h @@ -359,6 +359,7 @@ struct intel_engine_cs { unsigned int hw_id; unsigned int guc_id; unsigned long mask; + u32 watchdog_disable_id; u8 uabi_class; @@ -462,6 +463,7 @@ struct intel_engine_cs { int (*init_context)(struct i915_request *rq); int (*emit_flush)(struct i915_request *request, u32 mode); + #define EMIT_INVALIDATE BIT(0) #define EMIT_FLUSH BIT(1) #define EMIT_BARRIER (EMIT_INVALIDATE | EMIT_FLUSH) @@ -519,10 +521,12 @@ struct intel_engine_cs { struct intel_engine_hangcheck hangcheck; -#define I915_ENGINE_NEEDS_CMD_PARSER BIT(0) -#define I915_ENGINE_SUPPORTS_STATS BIT(1) -#define I915_ENGINE_HAS_PREEMPTION BIT(2) -#define I915_ENGINE_IS_VIRTUAL BIT(3) +#define I915_ENGINE_NEEDS_CMD_PARSER BIT(0) +#define I915_ENGINE_SUPPORTS_STATS BIT(1) +#define I915_ENGINE_HAS_PREEMPTION BIT(2) +#define I915_ENGINE_IS_VIRTUAL BIT(3) +#define I915_ENGINE_SUPPORTS_WATCHDOG BIT(4) + unsigned int flags; /* @@ -611,6 +615,12 @@ intel_engine_is_virtual(const struct intel_engine_cs *engine) return engine->flags & I915_ENGINE_IS_VIRTUAL; } +static inline bool +intel_engine_supports_watchdog(const struct intel_engine_cs *engine) +{ + return engine->flags & I915_ENGINE_SUPPORTS_WATCHDOG; +} + static inline void execlists_set_active(struct intel_engine_execlists *execlists, unsigned int bit)