From patchwork Thu Mar 7 20:32:39 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Gwan-gyeong Mun X-Patchwork-Id: 10843837 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 38AB8922 for ; Thu, 7 Mar 2019 20:32:55 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 271432F96F for ; Thu, 7 Mar 2019 20:32:55 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 1B30C2F981; Thu, 7 Mar 2019 20:32:55 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id A8BD22F96F for ; Thu, 7 Mar 2019 20:32:54 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id E45E76E22C; Thu, 7 Mar 2019 20:32:53 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTPS id 2DDDA6E22C for ; Thu, 7 Mar 2019 20:32:53 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 07 Mar 2019 12:32:53 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.58,453,1544515200"; d="scan'208";a="123589562" Received: from helsinki.fi.intel.com ([10.237.66.120]) by orsmga008.jf.intel.com with ESMTP; 07 Mar 2019 12:32:51 -0800 From: Gwan-gyeong Mun To: intel-gfx@lists.freedesktop.org Date: Thu, 7 Mar 2019 22:32:39 +0200 Message-Id: <20190307203240.31847-6-gwan-gyeong.mun@intel.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190307203240.31847-1-gwan-gyeong.mun@intel.com> References: <20190307203240.31847-1-gwan-gyeong.mun@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [RFC v5 5/6] drm/i915/dp: Change a link bandwidth computation for DP YCbCr 4:2:0 output X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP All of the link bandwidth and Data M/N calculations were assumed a bpp as RGB format. But When we are using YCbCr 4:2:0 output format on DP, we should change bpp calculations as YCbCr 4:2:0 format. The pipe_bpp value was assumed RGB format, therefore, it was multiplied with 3. But YCbCr 4:2:0 requires a multiplier value to 1.5. Therefore we need to divide pipe_bpp to 2 while DP output uses YCbCr4:2:0 format. - RGB format bpp = bpc x 3 - YCbCr 4:2:0 format bpp = bpc x 1.5 And it adds missed bpc values for a programming of VSC Header. It only affects dp and edp port which use YCbCr 4:2:0 output format. And for now, it does not consider a use case of DSC + YCbCr 4:2:0. v2: Addressed review comments from Ville. Remove a changing of pipe_bpp on intel_ddi_set_pipe_settings(). Because the pipe is running at the full bpp, keep pipe_bpp as RGB even though YCbCr 4:2:0 output format is used. Add a link bandwidth computation for YCbCr4:2:0 output format. v3: Addressed reivew comments from Ville. In order to make codes simple, it adds and uses intel_dp_output_bpp() function. Cc: Ville Syrjälä Signed-off-by: Gwan-gyeong Mun --- drivers/gpu/drm/i915/intel_dp.c | 45 ++++++++++++++++++++++++++++++--- 1 file changed, 41 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index c5219331539a..40135f98d164 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -1823,6 +1823,19 @@ intel_dp_adjust_compliance_config(struct intel_dp *intel_dp, } } +static int intel_dp_output_bpp(const struct intel_crtc_state *crtc_state, int bpp) +{ + /* + * bpp value was assumed to RGB format. And YCbCr 4:2:0 output + * format of the number of bytes per pixel will be half the number + * of bytes of RGB pixel. + */ + if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) + bpp /= 2; + + return bpp; +} + /* Optimize link config in order: max bpp, min clock, min lanes */ static int intel_dp_compute_link_config_wide(struct intel_dp *intel_dp, @@ -1834,8 +1847,10 @@ intel_dp_compute_link_config_wide(struct intel_dp *intel_dp, int mode_rate, link_clock, link_avail; for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) { + int output_bpp = intel_dp_output_bpp(pipe_config, bpp); + mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock, - bpp); + output_bpp); for (clock = limits->min_clock; clock <= limits->max_clock; clock++) { for (lane_count = limits->min_lane_count; @@ -1870,8 +1885,10 @@ intel_dp_compute_link_config_fast(struct intel_dp *intel_dp, int mode_rate, link_clock, link_avail; for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) { + int output_bpp = intel_dp_output_bpp(pipe_config, bpp); + mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock, - bpp); + output_bpp); for (lane_count = limits->min_lane_count; lane_count <= limits->max_lane_count; @@ -2220,13 +2237,16 @@ intel_dp_compute_config(struct intel_encoder *encoder, intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_LIMITED; } - if (!pipe_config->dsc_params.compression_enable) - intel_link_compute_m_n(pipe_config->pipe_bpp, + if (!pipe_config->dsc_params.compression_enable) { + int output_bpp = intel_dp_output_bpp(pipe_config, pipe_config->pipe_bpp); + + intel_link_compute_m_n(output_bpp, pipe_config->lane_count, adjusted_mode->crtc_clock, pipe_config->port_clock, &pipe_config->dp_m_n, constant_n); + } else intel_link_compute_m_n(pipe_config->dsc_params.compressed_bpp, pipe_config->lane_count, @@ -4454,6 +4474,23 @@ intel_pixel_encoding_setup_vsc(struct intel_dp *intel_dp, * 100b = 16bpc. */ vsc_sdp.DB17 = 0x1; + switch (crtc_state->pipe_bpp / 3) { + case 8: /* 8bpc */ + vsc_sdp.DB17 = 0x1; + break; + case 10: /* 10bpc */ + vsc_sdp.DB17 = 0x2; + break; + case 12: /* 12bpc */ + vsc_sdp.DB17 = 0x3; + break; + case 16: /* 16bpc */ + vsc_sdp.DB17 = 0x4; + break; + default: + DRM_DEBUG_KMS("Invalid bpp value '%d'\n", crtc_state->pipe_bpp); + break; + } /* * Content Type (Bits 2:0)