| Message ID | 20190313211144.4842-4-rodrigo.vivi@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [1/9] drm/i915/ehl: Add EHL platform info and PCI IDs | expand |
On Wed, 2019-03-13 at 14:11 -0700, Rodrigo Vivi wrote: > From: Lucas De Marchi <lucas.demarchi@intel.com> > > Elkhart Lake has a different set of PLLs as compared to Ice Lake, > although programming them is very similar. > Reviewed-by: José Roberto de Souza <jose.souza@intel.com> > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> > --- > drivers/gpu/drm/i915/intel_dpll_mgr.c | 16 +++++++++++++++- > 1 file changed, 15 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c > b/drivers/gpu/drm/i915/intel_dpll_mgr.c > index b3fb221c2532..a9feb119c19f 100644 > --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c > +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c > @@ -3246,6 +3246,18 @@ static const struct intel_dpll_mgr icl_pll_mgr > = { > .dump_hw_state = icl_dump_hw_state, > }; > > +static const struct dpll_info ehl_plls[] = { > + { "DPLL 0", &icl_pll_funcs, DPLL_ID_ICL_DPLL0, 0 }, > + { "DPLL 1", &icl_pll_funcs, DPLL_ID_ICL_DPLL1, 0 }, > + { }, > +}; > + > +static const struct intel_dpll_mgr ehl_pll_mgr = { > + .dpll_info = ehl_plls, > + .get_dpll = icl_get_dpll, > + .dump_hw_state = icl_dump_hw_state, > +}; > + > /** > * intel_shared_dpll_init - Initialize shared DPLLs > * @dev: drm device > @@ -3259,7 +3271,9 @@ void intel_shared_dpll_init(struct drm_device > *dev) > const struct dpll_info *dpll_info; > int i; > > - if (INTEL_GEN(dev_priv) >= 11) > + if (IS_ELKHARTLAKE(dev_priv)) > + dpll_mgr = &ehl_pll_mgr; > + else if (INTEL_GEN(dev_priv) >= 11) > dpll_mgr = &icl_pll_mgr; > else if (IS_CANNONLAKE(dev_priv)) > dpll_mgr = &cnl_pll_mgr;
diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c index b3fb221c2532..a9feb119c19f 100644 --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c @@ -3246,6 +3246,18 @@ static const struct intel_dpll_mgr icl_pll_mgr = { .dump_hw_state = icl_dump_hw_state, }; +static const struct dpll_info ehl_plls[] = { + { "DPLL 0", &icl_pll_funcs, DPLL_ID_ICL_DPLL0, 0 }, + { "DPLL 1", &icl_pll_funcs, DPLL_ID_ICL_DPLL1, 0 }, + { }, +}; + +static const struct intel_dpll_mgr ehl_pll_mgr = { + .dpll_info = ehl_plls, + .get_dpll = icl_get_dpll, + .dump_hw_state = icl_dump_hw_state, +}; + /** * intel_shared_dpll_init - Initialize shared DPLLs * @dev: drm device @@ -3259,7 +3271,9 @@ void intel_shared_dpll_init(struct drm_device *dev) const struct dpll_info *dpll_info; int i; - if (INTEL_GEN(dev_priv) >= 11) + if (IS_ELKHARTLAKE(dev_priv)) + dpll_mgr = &ehl_pll_mgr; + else if (INTEL_GEN(dev_priv) >= 11) dpll_mgr = &icl_pll_mgr; else if (IS_CANNONLAKE(dev_priv)) dpll_mgr = &cnl_pll_mgr;