| Message ID | 20190313211144.4842-7-rodrigo.vivi@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [1/9] drm/i915/ehl: Add EHL platform info and PCI IDs | expand |
On Wed, 2019-03-13 at 14:11 -0700, Rodrigo Vivi wrote: > From: Bob Paauwe <bob.j.paauwe@intel.com> > > EHL has a different number of subslices. > Reviewed-by: José Roberto de Souza <jose.souza@intel.com> > Cc: Lucas De Marchi <lucas.demarchi@intel.com> > Signed-off-by: Bob Paauwe <bob.j.paauwe@intel.com> > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> > --- > drivers/gpu/drm/i915/intel_device_info.c | 12 +++++++++--- > 1 file changed, 9 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_device_info.c > b/drivers/gpu/drm/i915/intel_device_info.c > index c8c0f4134bdb..31411f1cdbb4 100644 > --- a/drivers/gpu/drm/i915/intel_device_info.c > +++ b/drivers/gpu/drm/i915/intel_device_info.c > @@ -156,9 +156,15 @@ static void gen11_sseu_info_init(struct > drm_i915_private *dev_priv) > u8 eu_en; > int s; > > - sseu->max_slices = 1; > - sseu->max_subslices = 8; > - sseu->max_eus_per_subslice = 8; > + if (IS_ELKHARTLAKE(dev_priv)) { > + sseu->max_slices = 1; > + sseu->max_subslices = 4; > + sseu->max_eus_per_subslice = 8; > + } else { > + sseu->max_slices = 1; > + sseu->max_subslices = 8; > + sseu->max_eus_per_subslice = 8; > + } > > s_en = I915_READ(GEN11_GT_SLICE_ENABLE) & GEN11_GT_S_ENA_MASK; > ss_en = ~I915_READ(GEN11_GT_SUBSLICE_DISABLE);
On Wed, Mar 13, 2019 at 02:11:42PM -0700, Rodrigo Vivi wrote: >From: Bob Paauwe <bob.j.paauwe@intel.com> > >EHL has a different number of subslices. > >Cc: Lucas De Marchi <lucas.demarchi@intel.com> >Signed-off-by: Bob Paauwe <bob.j.paauwe@intel.com> >Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> >--- > drivers/gpu/drm/i915/intel_device_info.c | 12 +++++++++--- > 1 file changed, 9 insertions(+), 3 deletions(-) > >diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c >index c8c0f4134bdb..31411f1cdbb4 100644 >--- a/drivers/gpu/drm/i915/intel_device_info.c >+++ b/drivers/gpu/drm/i915/intel_device_info.c >@@ -156,9 +156,15 @@ static void gen11_sseu_info_init(struct drm_i915_private *dev_priv) > u8 eu_en; > int s; > >- sseu->max_slices = 1; >- sseu->max_subslices = 8; >- sseu->max_eus_per_subslice = 8; >+ if (IS_ELKHARTLAKE(dev_priv)) { >+ sseu->max_slices = 1; >+ sseu->max_subslices = 4; >+ sseu->max_eus_per_subslice = 8; matches spec. Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Lucas De Marchi >+ } else { >+ sseu->max_slices = 1; >+ sseu->max_subslices = 8; >+ sseu->max_eus_per_subslice = 8; >+ } > > s_en = I915_READ(GEN11_GT_SLICE_ENABLE) & GEN11_GT_S_ENA_MASK; > ss_en = ~I915_READ(GEN11_GT_SUBSLICE_DISABLE); >-- >2.20.1 >
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c index c8c0f4134bdb..31411f1cdbb4 100644 --- a/drivers/gpu/drm/i915/intel_device_info.c +++ b/drivers/gpu/drm/i915/intel_device_info.c @@ -156,9 +156,15 @@ static void gen11_sseu_info_init(struct drm_i915_private *dev_priv) u8 eu_en; int s; - sseu->max_slices = 1; - sseu->max_subslices = 8; - sseu->max_eus_per_subslice = 8; + if (IS_ELKHARTLAKE(dev_priv)) { + sseu->max_slices = 1; + sseu->max_subslices = 4; + sseu->max_eus_per_subslice = 8; + } else { + sseu->max_slices = 1; + sseu->max_subslices = 8; + sseu->max_eus_per_subslice = 8; + } s_en = I915_READ(GEN11_GT_SLICE_ENABLE) & GEN11_GT_S_ENA_MASK; ss_en = ~I915_READ(GEN11_GT_SUBSLICE_DISABLE);