diff mbox series

[20/30] drm/i915/guc: Make use of the SW counter field in the context descriptor

Message ID 20190329221118.17308-21-michal.wajdeczko@intel.com (mailing list archive)
State New, archived
Headers show
Series GuC 32.0.3 | expand

Commit Message

Michal Wajdeczko March 29, 2019, 10:11 p.m. UTC 
From: Oscar Mateo <oscar.mateo@intel.com>

The new context descriptor format contains two assignable fields:
the SW Context ID (technically 11 bits, but practically limited to 2032
entries due to some being reserved for future use by the GuC) and the
SW Counter (6 bits).

We don't want to limit ourselves too much in the maximum number of
concurrent contexts we want to allow, so ideally we want to employ
every possible bit available. Unfortunately, a further limitation in
the interface with the GuC means the combination of SW Context ID +
SW Counter has to be unique within the same engine class (as we use
the SW Context ID to index in the GuC stage descriptor pool, and the
Engine Class + SW Counter to index in the 2-dimensional lrc array).
This essentially means we need to somehow encode the engine instance.

Since the BSpec allows 6 bits for engine instance, we use the whole
SW counter for this task. If the limitation of 2032 maximum simultaneous
contexts is too restrictive, we can always squeeze things a bit more
(3 extras bits for hw_id, 3 bits for instance) and things will still
work (Gen11 does not instance more than 8 engines of any class).

Another alternative would be to generate the hw_id per HW context
instead of per GEM context, but that has other problems (e.g. maximum
number of user-created contexts would be variable, no relationship
between a GuC principal descriptor and the proxy descriptor it uses, ...)

Bspec: 12254

Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: Michal Winiarski <michal.winiarski@intel.com>
Cc: Tomasz Lis <tomasz.lis@intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h            |  9 ++++++++-
 drivers/gpu/drm/i915/i915_gem_context.c    |  6 +++++-
 drivers/gpu/drm/i915/i915_perf.c           |  1 +
 drivers/gpu/drm/i915/i915_reg.h            |  2 ++
 drivers/gpu/drm/i915/intel_context_types.h |  2 ++
 drivers/gpu/drm/i915/intel_lrc.c           | 12 +++++++++---
 6 files changed, 27 insertions(+), 5 deletions(-)

Comments

Chris Wilson March 29, 2019, 10:30 p.m. UTC | #1 
Quoting Michal Wajdeczko (2019-03-29 22:11:08)
> From: Oscar Mateo <oscar.mateo@intel.com>
> 
> The new context descriptor format contains two assignable fields:
> the SW Context ID (technically 11 bits, but practically limited to 2032
> entries due to some being reserved for future use by the GuC) and the
> SW Counter (6 bits).

Phooey, I've dropped use of the hw id. So no limit at all in execlists,
and no contention on pinning the hw id.

We could land that and move this mechanism to the guc backend so that it
doesn't impact anything else.
-Chris
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index f75600fa77c6..b3d5b715b637 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1758,14 +1758,21 @@  struct drm_i915_private {
 		struct llist_head free_list;
 		struct work_struct free_work;
 
-		/* The hw wants to have a stable context identifier for the
+		/*
+		 * The HW wants to have a stable context identifier for the
 		 * lifetime of the context (for OA, PASID, faults, etc).
 		 * This is limited in execlists to 21 bits.
+		 * In enhanced execlist (GEN11+) this is limited to 11 bits
+		 * (the SW Context ID field) but GuC limits it further so
+		 * without taking advantage of part of the SW counter field the
+		 * firmware only supports a max number of contexts equal to the
+		 * number of entries in the GuC stage descriptor pool.
 		 */
 		struct ida hw_ida;
 #define MAX_CONTEXT_HW_ID (1<<21) /* exclusive */
 #define MAX_GUC_CONTEXT_HW_ID (1 << 20) /* exclusive */
 #define GEN11_MAX_CONTEXT_HW_ID (1<<11) /* exclusive */
+#define GEN11_MAX_CONTEXT_HW_ID_WITH_GUC GUC_MAX_STAGE_DESCRIPTORS
 		struct list_head hw_id_list;
 	} contexts;
 
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
index 662da485e15f..d882525f67a3 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -144,8 +144,12 @@  static inline int new_hw_id(struct drm_i915_private *i915, gfp_t gfp)
 
 	lockdep_assert_held(&i915->contexts.mutex);
 
+	BUILD_BUG_ON(GUC_MAX_STAGE_DESCRIPTORS > GEN11_MAX_CONTEXT_HW_ID);
+
 	if (INTEL_GEN(i915) >= 11)
-		max = GEN11_MAX_CONTEXT_HW_ID;
+		max = USES_GUC_SUBMISSION(i915) ?
+		      GEN11_MAX_CONTEXT_HW_ID_WITH_GUC :
+		      GEN11_MAX_CONTEXT_HW_ID;
 	else if (USES_GUC_SUBMISSION(i915))
 		/*
 		 * When using GuC in proxy submission, GuC consumes the
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 39a4804091d7..08fb77333d85 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -1292,6 +1292,7 @@  static int oa_get_render_ctx_id(struct i915_perf_stream *stream)
 	case 11: {
 		i915->perf.oa.specific_ctx_id_mask =
 			((1U << GEN11_SW_CTX_ID_WIDTH) - 1) << (GEN11_SW_CTX_ID_SHIFT - 32) |
+			((1U << GEN11_SW_COUNTER_WIDTH) - 1) << (GEN11_SW_COUNTER_SHIFT - 32) |
 			((1U << GEN11_ENGINE_INSTANCE_WIDTH) - 1) << (GEN11_ENGINE_INSTANCE_SHIFT - 32) |
 			((1 << GEN11_ENGINE_CLASS_WIDTH) - 1) << (GEN11_ENGINE_CLASS_SHIFT - 32);
 		i915->perf.oa.specific_ctx_id = upper_32_bits(ce->lrc_desc);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 341f03e00536..8aee35ced574 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4008,6 +4008,8 @@  enum {
 #define GEN8_CTX_ID_WIDTH 21
 #define GEN11_SW_CTX_ID_SHIFT 37
 #define GEN11_SW_CTX_ID_WIDTH 11
+#define GEN11_SW_COUNTER_SHIFT 55
+#define GEN11_SW_COUNTER_WIDTH 6
 #define GEN11_ENGINE_CLASS_SHIFT 61
 #define GEN11_ENGINE_CLASS_WIDTH 3
 #define GEN11_ENGINE_INSTANCE_SHIFT 48
diff --git a/drivers/gpu/drm/i915/intel_context_types.h b/drivers/gpu/drm/i915/intel_context_types.h
index 624729a35875..af4183780271 100644
--- a/drivers/gpu/drm/i915/intel_context_types.h
+++ b/drivers/gpu/drm/i915/intel_context_types.h
@@ -53,6 +53,8 @@  struct intel_context {
 
 	u32 *lrc_reg_state;
 	u64 lrc_desc;
+	u32 sw_context_id;
+	u32 sw_counter;
 
 	atomic_t pin_count;
 	struct mutex pin_mutex; /* guards pinning and associated on-gpuing */
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index bec232acc8d7..31db38560680 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -345,14 +345,15 @@  lrc_descriptor(struct intel_context *ce, struct intel_engine_cs *engine)
 	 * anything below.
 	 */
 	if (INTEL_GEN(engine->i915) >= 11) {
-		GEM_BUG_ON(ctx->hw_id >= BIT(GEN11_SW_CTX_ID_WIDTH));
-		desc |= (u64)ctx->hw_id << GEN11_SW_CTX_ID_SHIFT;
+		GEM_BUG_ON(ce->sw_context_id >= BIT(GEN11_SW_CTX_ID_WIDTH));
+		desc |= (u64)ce->sw_context_id << GEN11_SW_CTX_ID_SHIFT;
 								/* bits 37-47 */
 
 		desc |= (u64)engine->instance << GEN11_ENGINE_INSTANCE_SHIFT;
 								/* bits 48-53 */
 
-		/* TODO: decide what to do with SW counter (bits 55-60) */
+		desc |= (u64)ce->sw_counter << GEN11_SW_COUNTER_SHIFT;
+								/* bits 55-60 */
 
 		desc |= (u64)engine->class << GEN11_ENGINE_CLASS_SHIFT;
 								/* bits 61-63 */
@@ -1358,6 +1359,11 @@  __execlists_context_pin(struct intel_context *ce,
 	if (ret)
 		goto unpin_ring;
 
+	if (INTEL_GEN(engine->i915) >= 11) {
+		ce->sw_context_id = ce->gem_context->hw_id;
+		ce->sw_counter = engine->instance;
+	}
+
 	ce->lrc_desc = lrc_descriptor(ce, engine);
 	ce->lrc_reg_state = vaddr + LRC_STATE_PN * PAGE_SIZE;
 	__execlists_update_reg_state(ce, engine);