From patchwork Fri Mar 29 22:11:14 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Wajdeczko X-Patchwork-Id: 10877861 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A252113B5 for ; Fri, 29 Mar 2019 22:12:30 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 8D20E28E8F for ; Fri, 29 Mar 2019 22:12:30 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 81AB0292AE; Fri, 29 Mar 2019 22:12:30 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 21F0F2906F for ; Fri, 29 Mar 2019 22:12:30 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id E47176E57D; Fri, 29 Mar 2019 22:12:21 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by gabe.freedesktop.org (Postfix) with ESMTPS id DE0116E569 for ; Fri, 29 Mar 2019 22:11:51 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga104.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 29 Mar 2019 15:11:51 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.60,286,1549958400"; d="scan'208";a="156522351" Received: from irvmail001.ir.intel.com ([163.33.26.43]) by fmsmga002.fm.intel.com with ESMTP; 29 Mar 2019 15:11:50 -0700 Received: from mwajdecz-MOBL1.ger.corp.intel.com (mwajdecz-mobl1.ger.corp.intel.com [10.249.137.139]) by irvmail001.ir.intel.com (8.14.3/8.13.6/MailSET/Hub) with ESMTP id x2TMBN0q017079; Fri, 29 Mar 2019 22:11:49 GMT From: Michal Wajdeczko To: intel-gfx@lists.freedesktop.org Date: Fri, 29 Mar 2019 22:11:14 +0000 Message-Id: <20190329221118.17308-27-michal.wajdeczko@intel.com> X-Mailer: git-send-email 2.10.1.windows.1 In-Reply-To: <20190329221118.17308-1-michal.wajdeczko@intel.com> References: <20190329221118.17308-1-michal.wajdeczko@intel.com> Subject: [Intel-gfx] [PATCH 26/30] drm/i915/guc: Properly capture & release GuC interrupts on Gen11 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Oscar Mateo MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP From: Oscar Mateo With the new interrupt re-partitioning in Gen11, GuC controls by itself the interrupts it receives, so steering bits and registers have been defeatured. Being this the case, when the GuC is in control of submissions we won't know what to do with the ctx switch interrupt in the driver, so disable it. Bspec: 12609 Bspec: 10800 Bspec: 10932 Bspec: 10934 Bspec: 9517 Signed-off-by: Oscar Mateo Signed-off-by: Michal Wajdeczko Cc: Daniele Ceraolo Spurio Cc: Joonas Lahtinen Cc: Michal Winiarski --- drivers/gpu/drm/i915/i915_irq.c | 2 +- drivers/gpu/drm/i915/intel_guc_submission.c | 57 ++++++++++++++++++++- 2 files changed, 56 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 455b2bf691b5..4de6474b6a25 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -4634,7 +4634,7 @@ void intel_irq_init(struct drm_i915_private *dev_priv) if (INTEL_GEN(dev_priv) <= 7) rps->pm_intrmsk_mbz |= GEN6_PM_RP_UP_EI_EXPIRED; - if (INTEL_GEN(dev_priv) >= 8) + if (INTEL_GEN(dev_priv) >= 8 && INTEL_GEN(dev_priv) < 11) rps->pm_intrmsk_mbz |= GEN8_PMINTR_DISABLE_REDIRECT_TO_GUC; if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) diff --git a/drivers/gpu/drm/i915/intel_guc_submission.c b/drivers/gpu/drm/i915/intel_guc_submission.c index b0b10cac9b9b..e3f6e2b1aa99 100644 --- a/drivers/gpu/drm/i915/intel_guc_submission.c +++ b/drivers/gpu/drm/i915/intel_guc_submission.c @@ -1263,7 +1263,7 @@ void intel_guc_submission_fini(struct intel_guc *guc) guc_stage_desc_pool_destroy(guc); } -static void guc_interrupts_capture(struct drm_i915_private *dev_priv) +static void gen8_guc_interrupts_capture(struct drm_i915_private *dev_priv) { struct intel_rps *rps = &dev_priv->gt_pm.rps; struct intel_engine_cs *engine; @@ -1308,7 +1308,7 @@ static void guc_interrupts_capture(struct drm_i915_private *dev_priv) rps->pm_intrmsk_mbz &= ~GEN8_PMINTR_DISABLE_REDIRECT_TO_GUC; } -static void guc_interrupts_release(struct drm_i915_private *dev_priv) +static void gen8_guc_interrupts_release(struct drm_i915_private *dev_priv) { struct intel_rps *rps = &dev_priv->gt_pm.rps; struct intel_engine_cs *engine; @@ -1333,6 +1333,59 @@ static void guc_interrupts_release(struct drm_i915_private *dev_priv) rps->pm_intrmsk_mbz &= ~ARAT_EXPIRED_INTRMSK; } +static void gen11_guc_interrupts_capture(struct drm_i915_private *dev_priv) +{ + struct intel_rps *rps = &dev_priv->gt_pm.rps; + u32 tmp; + u32 irqs = GT_CONTEXT_SWITCH_INTERRUPT; + + /* Don't handle ctx switch interrupt in GuC submission mode */ + tmp = I915_READ(GEN11_RENDER_COPY_INTR_ENABLE); + tmp &= ~(irqs << 16 | irqs); + I915_WRITE(GEN11_RENDER_COPY_INTR_ENABLE, tmp); + + tmp = I915_READ(GEN11_VCS_VECS_INTR_ENABLE); + tmp &= ~(irqs << 16 | irqs); + I915_WRITE(GEN11_VCS_VECS_INTR_ENABLE, tmp); + + /* GuC needs ARAT expired interrupt unmasked */ + rps->pm_intrmsk_mbz |= ARAT_EXPIRED_INTRMSK; +} + +static void gen11_guc_interrupts_release(struct drm_i915_private *dev_priv) +{ + struct intel_rps *rps = &dev_priv->gt_pm.rps; + u32 tmp; + u32 irqs = GT_CONTEXT_SWITCH_INTERRUPT; + + /* Handle ctx switch interrupts again */ + tmp = I915_READ(GEN11_RENDER_COPY_INTR_ENABLE); + tmp |= (irqs << 16 | irqs); + I915_WRITE(GEN11_RENDER_COPY_INTR_ENABLE, tmp); + + tmp = I915_READ(GEN11_VCS_VECS_INTR_ENABLE); + tmp |= (irqs << 16 | irqs); + I915_WRITE(GEN11_VCS_VECS_INTR_ENABLE, tmp); + + rps->pm_intrmsk_mbz &= ~ARAT_EXPIRED_INTRMSK; +} + +static void guc_interrupts_capture(struct drm_i915_private *i915) +{ + if (INTEL_GEN(i915) >= 11) + gen11_guc_interrupts_capture(i915); + else + gen8_guc_interrupts_capture(i915); +} + +static void guc_interrupts_release(struct drm_i915_private *i915) +{ + if (INTEL_GEN(i915) >= 11) + gen11_guc_interrupts_release(i915); + else + gen8_guc_interrupts_release(i915); +} + static void guc_submission_park(struct intel_engine_cs *engine) { intel_engine_unpin_breadcrumbs_irq(engine);