From patchwork Fri Mar 29 22:11:15 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Wajdeczko X-Patchwork-Id: 10877863 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 68DB917E0 for ; Fri, 29 Mar 2019 22:12:31 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 5345128E8F for ; Fri, 29 Mar 2019 22:12:31 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 47CF2292AE; Fri, 29 Mar 2019 22:12:31 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id C1DA028E8F for ; Fri, 29 Mar 2019 22:12:30 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 2538E6E553; Fri, 29 Mar 2019 22:12:22 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTPS id 410676E56C for ; Fri, 29 Mar 2019 22:11:54 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga101.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 29 Mar 2019 15:11:53 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.60,286,1549958400"; d="scan'208";a="287130582" Received: from irvmail001.ir.intel.com ([163.33.26.43]) by orsmga004.jf.intel.com with ESMTP; 29 Mar 2019 15:11:51 -0700 Received: from mwajdecz-MOBL1.ger.corp.intel.com (mwajdecz-mobl1.ger.corp.intel.com [10.249.137.139]) by irvmail001.ir.intel.com (8.14.3/8.13.6/MailSET/Hub) with ESMTP id x2TMBN0r017079; Fri, 29 Mar 2019 22:11:50 GMT From: Michal Wajdeczko To: intel-gfx@lists.freedesktop.org Date: Fri, 29 Mar 2019 22:11:15 +0000 Message-Id: <20190329221118.17308-28-michal.wajdeczko@intel.com> X-Mailer: git-send-email 2.10.1.windows.1 In-Reply-To: <20190329221118.17308-1-michal.wajdeczko@intel.com> References: <20190329221118.17308-1-michal.wajdeczko@intel.com> Subject: [Intel-gfx] [PATCH 27/30] drm/i915/guc: Create vfuncs for the GuC interrupts control functions X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Oscar Mateo MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP From: Oscar Mateo Controlling and handling of the GuC interrupts is Gen specific. Create virtual functions to avoid redundant runtime Gen checks. Gen-specific versions of these functions will follow. Signed-off-by: Oscar Mateo Signed-off-by: Michal Wajdeczko Cc: Rodrigo Vivi Cc: Tvrtko Ursulin Cc: Daniele Ceraolo Spurio Cc: Joonas Lahtinen --- drivers/gpu/drm/i915/i915_drv.h | 22 ++++++++++++++++++++++ drivers/gpu/drm/i915/i915_irq.c | 18 ++++++++++++------ drivers/gpu/drm/i915/intel_drv.h | 3 --- drivers/gpu/drm/i915/intel_guc.h | 1 - drivers/gpu/drm/i915/intel_uc.c | 6 +++--- 5 files changed, 37 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 3e7d0f3d2c82..120b0967c4e8 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1580,6 +1580,13 @@ struct drm_i915_private { u32 pm_guc_events; u32 pipestat_irq_mask[I915_MAX_PIPES]; + struct { + bool enabled; + void (*reset)(struct drm_i915_private *i915); + void (*enable)(struct drm_i915_private *i915); + void (*disable)(struct drm_i915_private *i915); + } guc_interrupts; + struct i915_hotplug hotplug; struct intel_fbc fbc; struct i915_drrs drrs; @@ -2716,6 +2723,21 @@ extern void intel_irq_fini(struct drm_i915_private *dev_priv); int intel_irq_install(struct drm_i915_private *dev_priv); void intel_irq_uninstall(struct drm_i915_private *dev_priv); +static inline void intel_reset_guc_interrupts(struct drm_i915_private *i915) +{ + i915->guc_interrupts.reset(i915); +} + +static inline void intel_enable_guc_interrupts(struct drm_i915_private *i915) +{ + i915->guc_interrupts.enable(i915); +} + +static inline void intel_disable_guc_interrupts(struct drm_i915_private *i915) +{ + i915->guc_interrupts.disable(i915); +} + static inline bool intel_gvt_active(struct drm_i915_private *dev_priv) { return dev_priv->gvt; diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 4de6474b6a25..3dd971c09d52 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -535,7 +535,7 @@ void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv) gen6_reset_rps_interrupts(dev_priv); } -void gen9_reset_guc_interrupts(struct drm_i915_private *dev_priv) +static void gen9_reset_guc_interrupts(struct drm_i915_private *dev_priv) { assert_rpm_wakelock_held(dev_priv); @@ -544,26 +544,26 @@ void gen9_reset_guc_interrupts(struct drm_i915_private *dev_priv) spin_unlock_irq(&dev_priv->irq_lock); } -void gen9_enable_guc_interrupts(struct drm_i915_private *dev_priv) +static void gen9_enable_guc_interrupts(struct drm_i915_private *dev_priv) { assert_rpm_wakelock_held(dev_priv); spin_lock_irq(&dev_priv->irq_lock); - if (!dev_priv->guc.interrupts_enabled) { + if (!dev_priv->guc_interrupts.enabled) { WARN_ON_ONCE(I915_READ(gen6_pm_iir(dev_priv)) & dev_priv->pm_guc_events); - dev_priv->guc.interrupts_enabled = true; + dev_priv->guc_interrupts.enabled = true; gen6_enable_pm_irq(dev_priv, dev_priv->pm_guc_events); } spin_unlock_irq(&dev_priv->irq_lock); } -void gen9_disable_guc_interrupts(struct drm_i915_private *dev_priv) +static void gen9_disable_guc_interrupts(struct drm_i915_private *dev_priv) { assert_rpm_wakelock_held(dev_priv); spin_lock_irq(&dev_priv->irq_lock); - dev_priv->guc.interrupts_enabled = false; + dev_priv->guc_interrupts.enabled = false; gen6_disable_pm_irq(dev_priv, dev_priv->pm_guc_events); @@ -4637,6 +4637,12 @@ void intel_irq_init(struct drm_i915_private *dev_priv) if (INTEL_GEN(dev_priv) >= 8 && INTEL_GEN(dev_priv) < 11) rps->pm_intrmsk_mbz |= GEN8_PMINTR_DISABLE_REDIRECT_TO_GUC; + if (INTEL_GEN(dev_priv) >= 9) { + dev_priv->guc_interrupts.reset = gen9_reset_guc_interrupts; + dev_priv->guc_interrupts.enable = gen9_enable_guc_interrupts; + dev_priv->guc_interrupts.disable = gen9_disable_guc_interrupts; + } + if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) dev->driver->get_vblank_counter = g4x_get_vblank_counter; else if (INTEL_GEN(dev_priv) >= 3) diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index f8c7b291fdc3..1739f2fe5288 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -1618,9 +1618,6 @@ void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv, u8 pipe_mask); void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv, u8 pipe_mask); -void gen9_reset_guc_interrupts(struct drm_i915_private *dev_priv); -void gen9_enable_guc_interrupts(struct drm_i915_private *dev_priv); -void gen9_disable_guc_interrupts(struct drm_i915_private *dev_priv); /* intel_crt.c */ bool intel_crt_port_enabled(struct drm_i915_private *dev_priv, diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h index a4bc3355a753..47ec353ac666 100644 --- a/drivers/gpu/drm/i915/intel_guc.h +++ b/drivers/gpu/drm/i915/intel_guc.h @@ -56,7 +56,6 @@ struct intel_guc { /* intel_guc_recv interrupt related state */ spinlock_t irq_lock; - bool interrupts_enabled; unsigned int msg_enabled_mask; struct ida client_ids; diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c index b516cc1ff18c..1e7ad200e761 100644 --- a/drivers/gpu/drm/i915/intel_uc.c +++ b/drivers/gpu/drm/i915/intel_uc.c @@ -223,7 +223,7 @@ static int guc_enable_communication(struct intel_guc *guc) { struct drm_i915_private *i915 = guc_to_i915(guc); - gen9_enable_guc_interrupts(i915); + intel_enable_guc_interrupts(i915); if (HAS_GUC_CT(i915)) return intel_guc_ct_enable(&guc->ct); @@ -240,7 +240,7 @@ static void guc_disable_communication(struct intel_guc *guc) if (HAS_GUC_CT(i915)) intel_guc_ct_disable(&guc->ct); - gen9_disable_guc_interrupts(i915); + intel_disable_guc_interrupts(i915); guc->send = intel_guc_send_nop; guc->handler = intel_guc_to_host_event_handler_nop; @@ -362,7 +362,7 @@ int intel_uc_init_hw(struct drm_i915_private *i915) GEM_BUG_ON(!HAS_GUC(i915)); - gen9_reset_guc_interrupts(i915); + intel_reset_guc_interrupts(i915); /* WaEnableuKernelHeaderValidFix:skl */ /* WaEnableGuCBootHashCheckNotSet:skl,bxt,kbl */