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[PULL] gvt-fixes

Message ID 20190402094037.GB2322@zhen-hp.sh.intel.com (mailing list archive)
State New, archived
Headers show
Series [PULL] gvt-fixes | expand

Pull-request

https://github.com/intel/gvt-linux.git tags/gvt-fixes-2019-04-02

Message

Zhenyu Wang April 2, 2019, 9:40 a.m. UTC
Hi,

Here's gvt-fixes for 5.1-rc4 which includes misc fixes for
vGPU display plane size calculation, shadow mm pin count,
error recovery path for workload create and one kerneldoc
fix which I missed to include before.

Thanks.
--
The following changes since commit 26cdaac4793c49357d2c731f2190632cefb7efb1:

  drm/i915/icl: Fix VEBOX mismatch BUG_ON() (2019-03-28 15:36:40 +0200)

are available in the Git repository at:

  https://github.com/intel/gvt-linux.git tags/gvt-fixes-2019-04-02

for you to fetch changes up to a14f068545cc13db9e0ad0ea451ec42e5abc97c0:

  drm/i915/gvt: Fix kerneldoc typo for intel_vgpu_emulate_hotplug (2019-03-29 10:31:15 +0800)

----------------------------------------------------------------
gvt-fixes-2019-04-02

- Fix shadow mm pin count (Yan)
- Fix cmd parser error path recover (Yan)
- Fix vGPU display plane size calculation (Xiong)
- Fix kerneldoc (Chris)

----------------------------------------------------------------
Chris Wilson (1):
      drm/i915/gvt: Fix kerneldoc typo for intel_vgpu_emulate_hotplug

Xiong Zhang (1):
      drm/i915/gvt: Correct the calculation of plane size

Yan Zhao (2):
      drm/i915/gvt: do not deliver a workload if its creation fails
      drm/i915/gvt: do not let pin count of shadow mm go negative

 drivers/gpu/drm/i915/gvt/display.c   | 2 +-
 drivers/gpu/drm/i915/gvt/dmabuf.c    | 8 ++------
 drivers/gpu/drm/i915/gvt/gtt.c       | 2 +-
 drivers/gpu/drm/i915/gvt/scheduler.c | 5 +++--
 4 files changed, 7 insertions(+), 10 deletions(-)

Comments

Rodrigo Vivi April 4, 2019, 12:12 a.m. UTC | #1
On Tue, Apr 02, 2019 at 05:40:37PM +0800, Zhenyu Wang wrote:
> 
> Hi,
> 
> Here's gvt-fixes for 5.1-rc4 which includes misc fixes for
> vGPU display plane size calculation, shadow mm pin count,
> error recovery path for workload create and one kerneldoc
> fix which I missed to include before.

dim: 000d38970e98 ("drm/i915/gvt: Correct the calculation of plane size"): Fixes: SHA1 needs at least 12 digits:
dim:     e546e281d33("drm/i915/gvt: Dmabuf support for GVT-g")
dim: ERROR: issues in commits detected, aborting

Is it something you could fix on your side without having
to by-pass dim this time?

Thanks,
Rodrigo.

> 
> Thanks.
> --
> The following changes since commit 26cdaac4793c49357d2c731f2190632cefb7efb1:
> 
>   drm/i915/icl: Fix VEBOX mismatch BUG_ON() (2019-03-28 15:36:40 +0200)
> 
> are available in the Git repository at:
> 
>   https://github.com/intel/gvt-linux.git tags/gvt-fixes-2019-04-02
> 
> for you to fetch changes up to a14f068545cc13db9e0ad0ea451ec42e5abc97c0:
> 
>   drm/i915/gvt: Fix kerneldoc typo for intel_vgpu_emulate_hotplug (2019-03-29 10:31:15 +0800)
> 
> ----------------------------------------------------------------
> gvt-fixes-2019-04-02
> 
> - Fix shadow mm pin count (Yan)
> - Fix cmd parser error path recover (Yan)
> - Fix vGPU display plane size calculation (Xiong)
> - Fix kerneldoc (Chris)
> 
> ----------------------------------------------------------------
> Chris Wilson (1):
>       drm/i915/gvt: Fix kerneldoc typo for intel_vgpu_emulate_hotplug
> 
> Xiong Zhang (1):
>       drm/i915/gvt: Correct the calculation of plane size
> 
> Yan Zhao (2):
>       drm/i915/gvt: do not deliver a workload if its creation fails
>       drm/i915/gvt: do not let pin count of shadow mm go negative
> 
>  drivers/gpu/drm/i915/gvt/display.c   | 2 +-
>  drivers/gpu/drm/i915/gvt/dmabuf.c    | 8 ++------
>  drivers/gpu/drm/i915/gvt/gtt.c       | 2 +-
>  drivers/gpu/drm/i915/gvt/scheduler.c | 5 +++--
>  4 files changed, 7 insertions(+), 10 deletions(-)
> 
> 
> -- 
> Open Source Technology Center, Intel ltd.
> 
> $gpg --keyserver wwwkeys.pgp.net --recv-keys 4D781827
Zhenyu Wang April 4, 2019, 12:32 a.m. UTC | #2
On 2019.04.03 17:12:37 -0700, Rodrigo Vivi wrote:
> On Tue, Apr 02, 2019 at 05:40:37PM +0800, Zhenyu Wang wrote:
> > 
> > Hi,
> > 
> > Here's gvt-fixes for 5.1-rc4 which includes misc fixes for
> > vGPU display plane size calculation, shadow mm pin count,
> > error recovery path for workload create and one kerneldoc
> > fix which I missed to include before.
> 
> dim: 000d38970e98 ("drm/i915/gvt: Correct the calculation of plane size"): Fixes: SHA1 needs at least 12 digits:
> dim:     e546e281d33("drm/i915/gvt: Dmabuf support for GVT-g")
> dim: ERROR: issues in commits detected, aborting
> 
> Is it something you could fix on your side without having
> to by-pass dim this time?
> 

Sorry about that, looks people still doesn't generate Fixes tag
properly. I'll fix that and resend.
Zhenyu Wang April 4, 2019, 12:39 a.m. UTC | #3
On 2019.04.03 17:12:37 -0700, Rodrigo Vivi wrote:
> On Tue, Apr 02, 2019 at 05:40:37PM +0800, Zhenyu Wang wrote:
> > 
> > Hi,
> > 
> > Here's gvt-fixes for 5.1-rc4 which includes misc fixes for
> > vGPU display plane size calculation, shadow mm pin count,
> > error recovery path for workload create and one kerneldoc
> > fix which I missed to include before.
> 
> dim: 000d38970e98 ("drm/i915/gvt: Correct the calculation of plane size"): Fixes: SHA1 needs at least 12 digits:
> dim:     e546e281d33("drm/i915/gvt: Dmabuf support for GVT-g")
> dim: ERROR: issues in commits detected, aborting
> 
> Is it something you could fix on your side without having
> to by-pass dim this time?
> 

Please re-pull this one.

Thanks
--
The following changes since commit 26cdaac4793c49357d2c731f2190632cefb7efb1:

  drm/i915/icl: Fix VEBOX mismatch BUG_ON() (2019-03-28 15:36:40 +0200)

are available in the Git repository at:

  https://github.com/intel/gvt-linux.git tags/gvt-fixes-2019-04-04

for you to fetch changes up to cf9ed66671ec5f6cacc7b6efbad9d7c9e5e31776:

  drm/i915/gvt: Fix kerneldoc typo for intel_vgpu_emulate_hotplug (2019-04-04 08:45:45 +0800)

----------------------------------------------------------------
gvt-fixes-2019-04-04

- Fix shadow mm pin count (Yan)
- Fix cmd parser error path recover (Yan)
- Fix vGPU display plane size calculation (Xiong)
- Fix kerneldoc (Chris)

----------------------------------------------------------------
Chris Wilson (1):
      drm/i915/gvt: Fix kerneldoc typo for intel_vgpu_emulate_hotplug

Xiong Zhang (1):
      drm/i915/gvt: Correct the calculation of plane size

Yan Zhao (2):
      drm/i915/gvt: do not deliver a workload if its creation fails
      drm/i915/gvt: do not let pin count of shadow mm go negative

 drivers/gpu/drm/i915/gvt/display.c   | 2 +-
 drivers/gpu/drm/i915/gvt/dmabuf.c    | 8 ++------
 drivers/gpu/drm/i915/gvt/gtt.c       | 2 +-
 drivers/gpu/drm/i915/gvt/scheduler.c | 5 +++--
 4 files changed, 7 insertions(+), 10 deletions(-)
Rodrigo Vivi April 4, 2019, 1:03 a.m. UTC | #4
On Thu, Apr 04, 2019 at 08:32:06AM +0800, Zhenyu Wang wrote:
> On 2019.04.03 17:12:37 -0700, Rodrigo Vivi wrote:
> > On Tue, Apr 02, 2019 at 05:40:37PM +0800, Zhenyu Wang wrote:
> > > 
> > > Hi,
> > > 
> > > Here's gvt-fixes for 5.1-rc4 which includes misc fixes for
> > > vGPU display plane size calculation, shadow mm pin count,
> > > error recovery path for workload create and one kerneldoc
> > > fix which I missed to include before.
> > 
> > dim: 000d38970e98 ("drm/i915/gvt: Correct the calculation of plane size"): Fixes: SHA1 needs at least 12 digits:
> > dim:     e546e281d33("drm/i915/gvt: Dmabuf support for GVT-g")
> > dim: ERROR: issues in commits detected, aborting
> > 
> > Is it something you could fix on your side without having
> > to by-pass dim this time?
> > 
> 
> Sorry about that, looks people still doesn't generate Fixes tag
> properly.

dim has a great helper for all developers to generate Fixes tags.

dim fixes <hash>

Besides the right tag it will also add right cc stable and other
cc folks.

We should advertise it more ;)

>  I'll fix that and resend.

I pulled the new one. Thanks for that.

> 
> -- 
> Open Source Technology Center, Intel ltd.
> 
> $gpg --keyserver wwwkeys.pgp.net --recv-keys 4D781827