drm/i915/ehl: Add support for DPLL4 (v2)

Commit Message

Vivek Kasireddy April 4, 2019, 11:22 p.m. UTC

This patch adds support for DPLL4 on EHL that include the
following restrictions:

- DPLL4 cannot be used with DDIA (combo port A internal eDP usage).
  DPLL4 can be used with other DDIs, including DDID
  (combo port A external usage).

- DPLL4 cannot be enabled when DC5 or DC6 are enabled.

- The DPLL4 enable, lock, power enabled, and power state are connected
  to the MGPLL1_ENABLE register.

v2: (suggestions from Bob Paauwe)
- Rework ehl_get_dpll() function to call intel_find_shared_dpll() and
  iterate twice: once for Combo plls and once for MG plls.

- Use MG pll funcs for DPLL4 instead of creating new ones and modify
  mg_pll_enable to include the restrictions for EHL.

Cc: Lucas De Marchi <[e-mail]>
Signed-off-by: Vivek Kasireddy <[e-mail]>
Reviewed-by: Bob Paauwe <[e-mail]>
---
 drivers/gpu/drm/i915/intel_dpll_mgr.c | 60 ++++++++++++++++++++++++++++++++++-
 1 file changed, 59 insertions(+), 1 deletion(-)

Comments

kernel test robot April 5, 2019, 4:23 a.m. UTC | #1

Hi Vivek,

Thank you for the patch! Yet something to improve:

[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on next-20190404]
[cannot apply to v5.1-rc3]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]

url:    https://github.com/0day-ci/linux/commits/Vivek-Kasireddy/drm-i915-ehl-Add-support-for-DPLL4-v2/20190405-110752
base:   git://anongit.freedesktop.org/drm-intel for-linux-next
config: x86_64-allyesconfig (attached as .config)
compiler: gcc-7 (Debian 7.3.0-1) 7.3.0
reproduce:
        # save the attached .config to linux build tree
        make ARCH=x86_64 

All errors (new ones prefixed by >>):

   drivers/gpu/drm/i915/intel_dpll_mgr.c: In function 'ehl_get_dpll':
>> drivers/gpu/drm/i915/intel_dpll_mgr.c:2907:8: error: too many arguments to function 'icl_calc_mg_pll_state'
     ret = icl_calc_mg_pll_state(crtc_state, false);
           ^~~~~~~~~~~~~~~~~~~~~
   drivers/gpu/drm/i915/intel_dpll_mgr.c:2649:13: note: declared here
    static bool icl_calc_mg_pll_state(struct intel_crtc_state *crtc_state)
                ^~~~~~~~~~~~~~~~~~~~~

vim +/icl_calc_mg_pll_state +2907 drivers/gpu/drm/i915/intel_dpll_mgr.c

  2872	
  2873	static struct intel_shared_dpll *
  2874	ehl_get_dpll(struct intel_crtc_state *crtc_state,
  2875		     struct intel_encoder *encoder)
  2876	{
  2877		struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
  2878		struct intel_shared_dpll *pll;
  2879		enum port port = encoder->port;
  2880		enum intel_dpll_id min, max;
  2881		bool ret;
  2882	
  2883		if (!intel_port_is_combophy(dev_priv, port)) {
  2884			MISSING_CASE(port);
  2885			return NULL;
  2886		}
  2887	
  2888		min = DPLL_ID_ICL_DPLL0;
  2889		max = DPLL_ID_ICL_DPLL1;
  2890		ret = icl_calc_dpll_state(crtc_state, encoder);
  2891		if (ret) {
  2892			pll = intel_find_shared_dpll(crtc_state, min, max);
  2893			if (pll) {
  2894				intel_reference_shared_dpll(pll, crtc_state);
  2895				return pll;
  2896			}
  2897		} else {
  2898			DRM_DEBUG_KMS("Could not calculate PLL state.\n");
  2899		}
  2900	
  2901		if (encoder->type == INTEL_OUTPUT_EDP) {
  2902			DRM_DEBUG_KMS("Cannot use DPLL4 with EDP.\n");
  2903			return NULL;
  2904		}
  2905	
  2906		min = max = DPLL_ID_ICL_MGPLL1;
> 2907		ret = icl_calc_mg_pll_state(crtc_state, false);
  2908		if (!ret) {
  2909			DRM_DEBUG_KMS("Could not calculate PLL state.\n");
  2910			return NULL;
  2911		}
  2912	
  2913		pll = intel_find_shared_dpll(crtc_state, min, max);
  2914		if (!pll) {
  2915			DRM_DEBUG_KMS("No PLL selected\n");
  2916			return NULL;
  2917		}
  2918	
  2919		intel_reference_shared_dpll(pll, crtc_state);
  2920		return pll;
  2921	}
  2922	

---
0-DAY kernel test infrastructure                Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all                   Intel Corporation

Patch

diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
index e01c057ce50b..cb756acedc94 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
@@ -2870,6 +2870,56 @@  icl_get_dpll(struct intel_crtc_state *crtc_state,
 	return pll;
 }
 
+static struct intel_shared_dpll *
+ehl_get_dpll(struct intel_crtc_state *crtc_state,
+	     struct intel_encoder *encoder)
+{
+	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
+	struct intel_shared_dpll *pll;
+	enum port port = encoder->port;
+	enum intel_dpll_id min, max;
+	bool ret;
+
+	if (!intel_port_is_combophy(dev_priv, port)) {
+		MISSING_CASE(port);
+		return NULL;
+	}
+
+	min = DPLL_ID_ICL_DPLL0;
+	max = DPLL_ID_ICL_DPLL1;
+	ret = icl_calc_dpll_state(crtc_state, encoder);
+	if (ret) {
+		pll = intel_find_shared_dpll(crtc_state, min, max);
+		if (pll) {
+			intel_reference_shared_dpll(pll, crtc_state);
+			return pll;
+		}
+	} else {
+		DRM_DEBUG_KMS("Could not calculate PLL state.\n");
+	}
+
+	if (encoder->type == INTEL_OUTPUT_EDP) {
+		DRM_DEBUG_KMS("Cannot use DPLL4 with EDP.\n");
+		return NULL;
+	}
+
+	min = max = DPLL_ID_ICL_MGPLL1;
+	ret = icl_calc_mg_pll_state(crtc_state, false);
+	if (!ret) {
+		DRM_DEBUG_KMS("Could not calculate PLL state.\n");
+		return NULL;
+	}
+
+	pll = intel_find_shared_dpll(crtc_state, min, max);
+	if (!pll) {
+		DRM_DEBUG_KMS("No PLL selected\n");
+		return NULL;
+	}
+
+	intel_reference_shared_dpll(pll, crtc_state);
+	return pll;
+}
+
 static bool mg_pll_get_hw_state(struct drm_i915_private *dev_priv,
 				struct intel_shared_dpll *pll,
 				struct intel_dpll_hw_state *hw_state)
@@ -3115,6 +3165,13 @@  static void mg_pll_enable(struct drm_i915_private *dev_priv,
 	i915_reg_t enable_reg =
 		MG_PLL_ENABLE(icl_pll_id_to_tc_port(pll->info->id));
 
+	if (IS_ELKHARTLAKE(dev_priv) &&
+	   (I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5 ||
+	    I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC6)) {
+		DRM_ERROR("Cant enable DPLL4 when DC5 or DC6 are enabled\n");
+		return;
+	}
+
 	icl_pll_power_enable(dev_priv, pll, enable_reg);
 
 	icl_mg_pll_write(dev_priv, pll);
@@ -3249,12 +3306,13 @@  static const struct intel_dpll_mgr icl_pll_mgr = {
 static const struct dpll_info ehl_plls[] = {
 	{ "DPLL 0", &combo_pll_funcs, DPLL_ID_ICL_DPLL0, 0 },
 	{ "DPLL 1", &combo_pll_funcs, DPLL_ID_ICL_DPLL1, 0 },
+	{ "DPLL 4", &mg_pll_funcs, DPLL_ID_ICL_MGPLL1,0 },
 	{ },
 };
 
 static const struct intel_dpll_mgr ehl_pll_mgr = {
 	.dpll_info = ehl_plls,
-	.get_dpll = icl_get_dpll,
+	.get_dpll = ehl_get_dpll,
 	.dump_hw_state = icl_dump_hw_state,
 };