From patchwork Tue Apr 9 00:37:28 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Zanoni, Paulo R" X-Patchwork-Id: 10890335 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 46F8E1669 for ; Tue, 9 Apr 2019 00:37:51 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 33C722850F for ; Tue, 9 Apr 2019 00:37:51 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 2861628793; Tue, 9 Apr 2019 00:37:51 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id A16C82850F for ; Tue, 9 Apr 2019 00:37:50 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 2721589170; Tue, 9 Apr 2019 00:37:50 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by gabe.freedesktop.org (Postfix) with ESMTPS id 5BCED89170 for ; Tue, 9 Apr 2019 00:37:49 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga104.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 08 Apr 2019 17:37:49 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.60,327,1549958400"; d="scan'208";a="162572820" Received: from przanoni-mobl.jf.intel.com ([10.24.11.95]) by fmsmga001.fm.intel.com with ESMTP; 08 Apr 2019 17:37:48 -0700 From: Paulo Zanoni To: intel-gfx@lists.freedesktop.org Date: Mon, 8 Apr 2019 17:37:28 -0700 Message-Id: <20190409003729.20857-3-paulo.r.zanoni@intel.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190409003729.20857-1-paulo.r.zanoni@intel.com> References: <20190409003729.20857-1-paulo.r.zanoni@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 2/3] drm/i915: convert the IRQ initialization functions to intel_uncore X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paulo Zanoni Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP The IRQ initialization helpers are simple and self-contained. Continue the transition started in the recent uncore rework to get us rid of I915_READ/WRITE and the implicit dev_priv variables. While the implicit dev_priv is removed from the IRQ initialization helpers, we didn't get rid of them in the macro callers. Doing that should be very simple now. Signed-off-by: Paulo Zanoni --- drivers/gpu/drm/i915/i915_irq.c | 100 ++++++++++++++++---------------- 1 file changed, 50 insertions(+), 50 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index a1e7944fb5d0..99a6527568cf 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -136,115 +136,115 @@ static const u32 hpd_icp[HPD_NUM_PINS] = { [HPD_PORT_F] = SDE_TC4_HOTPLUG_ICP }; -static void gen3_irq_reset(struct drm_i915_private *dev_priv, i915_reg_t imr, +static void gen3_irq_reset(struct intel_uncore *uncore, i915_reg_t imr, i915_reg_t iir, i915_reg_t ier) { - I915_WRITE(imr, 0xffffffff); - POSTING_READ(imr); + intel_uncore_write(uncore, imr, 0xffffffff); + intel_uncore_posting_read(uncore, imr); - I915_WRITE(ier, 0); + intel_uncore_write(uncore, ier, 0); /* IIR can theoretically queue up two events. Be paranoid. */ - I915_WRITE(iir, 0xffffffff); - POSTING_READ(iir); - I915_WRITE(iir, 0xffffffff); - POSTING_READ(iir); + intel_uncore_write(uncore, iir, 0xffffffff); + intel_uncore_posting_read(uncore, iir); + intel_uncore_write(uncore, iir, 0xffffffff); + intel_uncore_posting_read(uncore, iir); } -static void gen2_irq_reset(struct drm_i915_private *dev_priv, i915_reg_t imr, +static void gen2_irq_reset(struct intel_uncore *uncore, i915_reg_t imr, i915_reg_t iir, i915_reg_t ier) { - I915_WRITE16(imr, 0xffff); - POSTING_READ16(imr); + intel_uncore_write16(uncore, imr, 0xffff); + intel_uncore_posting_read16(uncore, imr); - I915_WRITE16(ier, 0); + intel_uncore_write16(uncore, ier, 0); /* IIR can theoretically queue up two events. Be paranoid. */ - I915_WRITE16(iir, 0xffff); - POSTING_READ16(iir); - I915_WRITE16(iir, 0xffff); - POSTING_READ16(iir); + intel_uncore_write16(uncore, iir, 0xffff); + intel_uncore_posting_read16(uncore, iir); + intel_uncore_write16(uncore, iir, 0xffff); + intel_uncore_posting_read16(uncore, iir); } #define GEN8_IRQ_RESET_NDX(type, which) \ - gen3_irq_reset(dev_priv, GEN8_##type##_IMR(which), \ + gen3_irq_reset(&dev_priv->uncore, GEN8_##type##_IMR(which), \ GEN8_##type##_IIR(which), GEN8_##type##_IER(which)) #define GEN3_IRQ_RESET(type) \ - gen3_irq_reset(dev_priv, type##IMR, type##IIR, type##IER) + gen3_irq_reset(&dev_priv->uncore, type##IMR, type##IIR, type##IER) #define GEN2_IRQ_RESET(type) \ - gen2_irq_reset(dev_priv, type##IMR, type##IIR, type##IER) + gen2_irq_reset(&dev_priv->uncore, type##IMR, type##IIR, type##IER) /* * We should clear IMR at preinstall/uninstall, and just check at postinstall. */ -static void gen3_assert_iir_is_zero(struct drm_i915_private *dev_priv, +static void gen3_assert_iir_is_zero(struct intel_uncore *uncore, i915_reg_t reg) { - u32 val = I915_READ(reg); + u32 val = intel_uncore_read(uncore, reg); if (val == 0) return; WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n", i915_mmio_reg_offset(reg), val); - I915_WRITE(reg, 0xffffffff); - POSTING_READ(reg); - I915_WRITE(reg, 0xffffffff); - POSTING_READ(reg); + intel_uncore_write(uncore, reg, 0xffffffff); + intel_uncore_posting_read(uncore, reg); + intel_uncore_write(uncore, reg, 0xffffffff); + intel_uncore_posting_read(uncore, reg); } -static void gen2_assert_iir_is_zero(struct drm_i915_private *dev_priv, +static void gen2_assert_iir_is_zero(struct intel_uncore *uncore, i915_reg_t reg) { - u16 val = I915_READ16(reg); + u16 val = intel_uncore_read16(uncore, reg); if (val == 0) return; WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n", i915_mmio_reg_offset(reg), val); - I915_WRITE16(reg, 0xffff); - POSTING_READ16(reg); - I915_WRITE16(reg, 0xffff); - POSTING_READ16(reg); + intel_uncore_write16(uncore, reg, 0xffff); + intel_uncore_posting_read16(uncore, reg); + intel_uncore_write16(uncore, reg, 0xffff); + intel_uncore_posting_read16(uncore, reg); } -static void gen3_irq_init(struct drm_i915_private *dev_priv, i915_reg_t imr, +static void gen3_irq_init(struct intel_uncore *uncore, i915_reg_t imr, i915_reg_t iir, i915_reg_t ier, u32 imr_val, u32 ier_val) { - gen3_assert_iir_is_zero(dev_priv, iir); + gen3_assert_iir_is_zero(uncore, iir); - I915_WRITE(ier, ier_val); - I915_WRITE(imr, imr_val); - POSTING_READ(imr); + intel_uncore_write(uncore, ier, ier_val); + intel_uncore_write(uncore, imr, imr_val); + intel_uncore_posting_read(uncore, imr); } -static void gen2_irq_init(struct drm_i915_private *dev_priv, i915_reg_t imr, +static void gen2_irq_init(struct intel_uncore *uncore, i915_reg_t imr, i915_reg_t iir, i915_reg_t ier, u32 imr_val, u32 ier_val) { - gen2_assert_iir_is_zero(dev_priv, iir); + gen2_assert_iir_is_zero(uncore, iir); - I915_WRITE16(ier, ier_val); - I915_WRITE16(imr, imr_val); - POSTING_READ16(imr); + intel_uncore_write16(uncore, ier, ier_val); + intel_uncore_write16(uncore, imr, imr_val); + intel_uncore_posting_read16(uncore, imr); } #define GEN8_IRQ_INIT_NDX(type, which, imr_val, ier_val) \ - gen3_irq_init(dev_priv, GEN8_##type##_IMR(which), \ + gen3_irq_init(&dev_priv->uncore, GEN8_##type##_IMR(which), \ GEN8_##type##_IIR(which), GEN8_##type##_IER(which), \ imr_val, ier_val) #define GEN3_IRQ_INIT(type, imr_val, ier_val) \ - gen3_irq_init(dev_priv, type##IMR, type##IIR, type##IER, imr_val, \ - ier_val) + gen3_irq_init(&dev_priv->uncore, type##IMR, type##IIR, type##IER, \ + imr_val, ier_val) #define GEN2_IRQ_INIT(type, imr_val, ier_val) \ - gen2_irq_init(dev_priv, type##IMR, type##IIR, type##IER, imr_val, \ - ier_val) + gen2_irq_init(&dev_priv->uncore, type##IMR, type##IIR, type##IER, \ + imr_val, ier_val) static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir); static void gen9_guc_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir); @@ -3849,7 +3849,7 @@ static void ibx_irq_postinstall(struct drm_device *dev) else mask = SDE_GMBUS_CPT; - gen3_assert_iir_is_zero(dev_priv, SDEIIR); + gen3_assert_iir_is_zero(&dev_priv->uncore, SDEIIR); I915_WRITE(SDEIMR, ~mask); if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) || @@ -3918,7 +3918,7 @@ static int ironlake_irq_postinstall(struct drm_device *dev) } if (IS_HASWELL(dev_priv)) { - gen3_assert_iir_is_zero(dev_priv, EDP_PSR_IIR); + gen3_assert_iir_is_zero(&dev_priv->uncore, EDP_PSR_IIR); intel_psr_irq_control(dev_priv, dev_priv->psr.debug); display_mask |= DE_EDP_PSR_INT_HSW; } @@ -4064,7 +4064,7 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv) else if (IS_BROADWELL(dev_priv)) de_port_enables |= GEN8_PORT_DP_A_HOTPLUG; - gen3_assert_iir_is_zero(dev_priv, EDP_PSR_IIR); + gen3_assert_iir_is_zero(&dev_priv->uncore, EDP_PSR_IIR); intel_psr_irq_control(dev_priv, dev_priv->psr.debug); for_each_pipe(dev_priv, pipe) { @@ -4148,7 +4148,7 @@ static void icp_irq_postinstall(struct drm_device *dev) I915_WRITE(SDEIER, 0xffffffff); POSTING_READ(SDEIER); - gen3_assert_iir_is_zero(dev_priv, SDEIIR); + gen3_assert_iir_is_zero(&dev_priv->uncore, SDEIIR); I915_WRITE(SDEIMR, ~mask); icp_hpd_detection_setup(dev_priv);