diff mbox series

[2/7] drm/i915/icl: Apply a recommended rc6 threshold

Message ID 20190409161310.20382-2-mika.kuoppala@linux.intel.com (mailing list archive)
State New, archived
Headers show
Series [1/7] drm/i915: Use dedicated rc6 enabling sequence for gen11 | expand

Commit Message

Mika Kuoppala April 9, 2019, 4:13 p.m. UTC
On gen11 the recommended rc6 threshold differs from previous
gens, apply it.

References: bspec#52070
Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Comments

Michal Wajdeczko April 9, 2019, 4:51 p.m. UTC | #1
On Tue, 09 Apr 2019 18:13:05 +0200, Mika Kuoppala  
<mika.kuoppala@linux.intel.com> wrote:

> On gen11 the recommended rc6 threshold differs from previous
> gens, apply it.
>
> References: bspec#52070

Is this correct number? I found it at 33149
And note that we are using different tag:

Bspec: 33149

> Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_pm.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c  
> b/drivers/gpu/drm/i915/intel_pm.c
> index 43ec0fb4c197..30ef507b88a4 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -7174,7 +7174,7 @@ static void gen11_enable_rc6(struct  
> drm_i915_private *dev_priv)
>  	I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 250);
> 	/* 3a: Enable RC6 */
> -	I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
> +	I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */

Btw, in bspec this is done at the end of step 2b.
Shall we reorder whole function to match the spec?

~Michal
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 43ec0fb4c197..30ef507b88a4 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -7174,7 +7174,7 @@  static void gen11_enable_rc6(struct drm_i915_private *dev_priv)
 	I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 250);
 
 	/* 3a: Enable RC6 */
-	I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
+	I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
 
 	I915_WRITE(GEN6_RC_CONTROL,
 		   GEN6_RC_CTL_HW_ENABLE |