diff mbox series

[2/7] drm/i915/icl: Apply a recommended rc6 threshold

Message ID 20190410105923.18546-2-mika.kuoppala@linux.intel.com (mailing list archive)
State New, archived
Headers show
Series [1/7] drm/i915: Use dedicated rc6 enabling sequence for gen11 | expand

Commit Message

Mika Kuoppala April 10, 2019, 10:59 a.m. UTC
On gen11 the recommended rc6 threshold differs from previous
gens, apply it. Move the write to a correct spot in sequence.

v2: do write in 2b, fix bspec ref (Michal)

Bspec: 33149
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

Comments

Chris Wilson April 10, 2019, 1:37 p.m. UTC | #1
Quoting Mika Kuoppala (2019-04-10 11:59:18)
> On gen11 the recommended rc6 threshold differs from previous
> gens, apply it. Move the write to a correct spot in sequence.
> 
> v2: do write in 2b, fix bspec ref (Michal)

Yes, it does make more sense not to include it as part of the 'rc6
enabling sequence' but as setup.

> Bspec: 33149
> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
> Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
-Chris
Michal Wajdeczko April 10, 2019, 1:53 p.m. UTC | #2
On Wed, 10 Apr 2019 12:59:18 +0200, Mika Kuoppala  
<mika.kuoppala@linux.intel.com> wrote:

> On gen11 the recommended rc6 threshold differs from previous
> gens, apply it. Move the write to a correct spot in sequence.
>
> v2: do write in 2b, fix bspec ref (Michal)
>
> Bspec: 33149
> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
> Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>

Full sequence still slightly differs compared to the spec,
but that's other story.

Reviewed-by: Michal Wajdeczko <michal.wajdeczko@intel.com>

~Michal
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 43ec0fb4c197..3a157bdbee2a 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -7149,6 +7149,8 @@  static void gen11_enable_rc6(struct drm_i915_private *dev_priv)
 
 	I915_WRITE(GEN6_RC_SLEEP, 0);
 
+	I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
+
 	/*
 	 * 2c: Program Coarse Power Gating Policies.
 	 *
@@ -7174,8 +7176,6 @@  static void gen11_enable_rc6(struct drm_i915_private *dev_priv)
 	I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 250);
 
 	/* 3a: Enable RC6 */
-	I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
-
 	I915_WRITE(GEN6_RC_CONTROL,
 		   GEN6_RC_CTL_HW_ENABLE |
 		   GEN6_RC_CTL_RC6_ENABLE |