diff mbox series

[v2,06/22] drm/i915/guc: Update GuC boot parameters

Message ID 20190411084436.24384-7-michal.wajdeczko@intel.com (mailing list archive)
State New, archived
Headers show
Series GuC 32.0.3 | expand

Commit Message

Michal Wajdeczko April 11, 2019, 8:44 a.m. UTC 
New GuC firmwares require updated boot parameters.

Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: John Spotswood <john.a.spotswood@intel.com>
---
 drivers/gpu/drm/i915/intel_guc.c      | 36 +++++++++----------------
 drivers/gpu/drm/i915/intel_guc_fwif.h | 39 +++++++--------------------
 2 files changed, 22 insertions(+), 53 deletions(-)

Comments

Daniele Ceraolo Spurio April 12, 2019, 11:46 p.m. UTC | #1 
On 4/11/19 1:44 AM, Michal Wajdeczko wrote:
> New GuC firmwares require updated boot parameters.
> 

Matches the FW headers.

Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>

Daniele

> Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Cc: John Spotswood <john.a.spotswood@intel.com>
> ---
>   drivers/gpu/drm/i915/intel_guc.c      | 36 +++++++++----------------
>   drivers/gpu/drm/i915/intel_guc_fwif.h | 39 +++++++--------------------
>   2 files changed, 22 insertions(+), 53 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c
> index c0e8b359b23a..483c7019f817 100644
> --- a/drivers/gpu/drm/i915/intel_guc.c
> +++ b/drivers/gpu/drm/i915/intel_guc.c
> @@ -243,14 +243,7 @@ void intel_guc_fini(struct intel_guc *guc)
>   static u32 guc_ctl_debug_flags(struct intel_guc *guc)
>   {
>   	u32 level = intel_guc_log_get_level(&guc->log);
> -	u32 flags;
> -	u32 ads;
> -
> -	ads = intel_guc_ggtt_offset(guc, guc->ads_vma) >> PAGE_SHIFT;
> -	flags = ads << GUC_ADS_ADDR_SHIFT | GUC_ADS_ENABLED;
> -
> -	if (!GUC_LOG_LEVEL_IS_ENABLED(level))
> -		flags |= GUC_LOG_DEFAULT_DISABLED;
> +	u32 flags = 0;
>   
>   	if (!GUC_LOG_LEVEL_IS_VERBOSE(level))
>   		flags |= GUC_LOG_DISABLED;
> @@ -265,11 +258,7 @@ static u32 guc_ctl_feature_flags(struct intel_guc *guc)
>   {
>   	u32 flags = 0;
>   
> -	flags |=  GUC_CTL_VCS2_ENABLED;
> -
> -	if (USES_GUC_SUBMISSION(guc_to_i915(guc)))
> -		flags |= GUC_CTL_KERNEL_SUBMISSIONS;
> -	else
> +	if (!USES_GUC_SUBMISSION(guc_to_i915(guc)))
>   		flags |= GUC_CTL_DISABLE_SCHEDULER;
>   
>   	return flags;
> @@ -333,22 +322,21 @@ static u32 guc_ctl_log_params_flags(struct intel_guc *guc)
>   	return flags;
>   }
>   
> -static void guc_prepare_params(struct intel_guc *guc, u32 *params)
> +static u32 guc_ctl_ads_flags(struct intel_guc *guc)
>   {
> -	/*
> -	 * GuC ARAT increment is 10 ns. GuC default scheduler quantum is one
> -	 * second. This ARAR is calculated by:
> -	 * Scheduler-Quantum-in-ns / ARAT-increment-in-ns = 1000000000 / 10
> -	 */
> -	params[GUC_CTL_ARAT_HIGH] = 0;
> -	params[GUC_CTL_ARAT_LOW] = 100000000;
> +	u32 ads = intel_guc_ggtt_offset(guc, guc->ads_vma) >> PAGE_SHIFT;
> +	u32 flags = ads << GUC_ADS_ADDR_SHIFT;
>   
> -	params[GUC_CTL_WA] |= GUC_CTL_WA_UK_BY_DRIVER;
> +	return flags;
> +}
>   
> +static void guc_prepare_params(struct intel_guc *guc, u32 *params)
> +{
> +	params[GUC_CTL_CTXINFO] = guc_ctl_ctxinfo_flags(guc);
> +	params[GUC_CTL_LOG_PARAMS] = guc_ctl_log_params_flags(guc);
>   	params[GUC_CTL_FEATURE] = guc_ctl_feature_flags(guc);
> -	params[GUC_CTL_LOG_PARAMS]  = guc_ctl_log_params_flags(guc);
>   	params[GUC_CTL_DEBUG] = guc_ctl_debug_flags(guc);
> -	params[GUC_CTL_CTXINFO] = guc_ctl_ctxinfo_flags(guc);
> +	params[GUC_CTL_ADS] = guc_ctl_ads_flags(guc);
>   }
>   
>   static void guc_write_params(struct intel_guc *guc, const u32 *params)
> diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h b/drivers/gpu/drm/i915/intel_guc_fwif.h
> index 1cb4fad2d539..64b56da9775c 100644
> --- a/drivers/gpu/drm/i915/intel_guc_fwif.h
> +++ b/drivers/gpu/drm/i915/intel_guc_fwif.h
> @@ -73,44 +73,28 @@
>   #define GUC_STAGE_DESC_ATTR_PCH		BIT(6)
>   #define GUC_STAGE_DESC_ATTR_TERMINATED	BIT(7)
>   
> -/* The guc control data is 10 DWORDs */
> +/* New GuC control data */
>   #define GUC_CTL_CTXINFO			0
>   #define   GUC_CTL_CTXNUM_IN16_SHIFT	0
>   #define   GUC_CTL_BASE_ADDR_SHIFT	12
>   
> -#define GUC_CTL_ARAT_HIGH		1
> -#define GUC_CTL_ARAT_LOW		2
> -
> -#define GUC_CTL_DEVICE_INFO		3
> -
> -#define GUC_CTL_LOG_PARAMS		4
> +#define GUC_CTL_LOG_PARAMS		1
>   #define   GUC_LOG_VALID			(1 << 0)
>   #define   GUC_LOG_NOTIFY_ON_HALF_FULL	(1 << 1)
>   #define   GUC_LOG_ALLOC_IN_MEGABYTE	(1 << 3)
>   #define   GUC_LOG_CRASH_SHIFT		4
> -#define   GUC_LOG_CRASH_MASK		(0x1 << GUC_LOG_CRASH_SHIFT)
> +#define   GUC_LOG_CRASH_MASK		(0x3 << GUC_LOG_CRASH_SHIFT)
>   #define   GUC_LOG_DPC_SHIFT		6
>   #define   GUC_LOG_DPC_MASK	        (0x7 << GUC_LOG_DPC_SHIFT)
>   #define   GUC_LOG_ISR_SHIFT		9
>   #define   GUC_LOG_ISR_MASK	        (0x7 << GUC_LOG_ISR_SHIFT)
>   #define   GUC_LOG_BUF_ADDR_SHIFT	12
>   
> -#define GUC_CTL_PAGE_FAULT_CONTROL	5
> -
> -#define GUC_CTL_WA			6
> -#define   GUC_CTL_WA_UK_BY_DRIVER	(1 << 3)
> -
> -#define GUC_CTL_FEATURE			7
> -#define   GUC_CTL_VCS2_ENABLED		(1 << 0)
> -#define   GUC_CTL_KERNEL_SUBMISSIONS	(1 << 1)
> -#define   GUC_CTL_FEATURE2		(1 << 2)
> -#define   GUC_CTL_POWER_GATING		(1 << 3)
> -#define   GUC_CTL_DISABLE_SCHEDULER	(1 << 4)
> -#define   GUC_CTL_PREEMPTION_LOG	(1 << 5)
> -#define   GUC_CTL_ENABLE_SLPC		(1 << 7)
> -#define   GUC_CTL_RESET_ON_PREMPT_FAILURE	(1 << 8)
> +#define GUC_CTL_WA			2
> +#define GUC_CTL_FEATURE			3
> +#define   GUC_CTL_DISABLE_SCHEDULER	(1 << 14)
>   
> -#define GUC_CTL_DEBUG			8
> +#define GUC_CTL_DEBUG			4
>   #define   GUC_LOG_VERBOSITY_SHIFT	0
>   #define   GUC_LOG_VERBOSITY_LOW		(0 << GUC_LOG_VERBOSITY_SHIFT)
>   #define   GUC_LOG_VERBOSITY_MED		(1 << GUC_LOG_VERBOSITY_SHIFT)
> @@ -123,13 +107,10 @@
>   #define	  GUC_LOG_DESTINATION_MASK	(3 << 4)
>   #define   GUC_LOG_DISABLED		(1 << 6)
>   #define   GUC_PROFILE_ENABLED		(1 << 7)
> -#define   GUC_WQ_TRACK_ENABLED		(1 << 8)
> -#define   GUC_ADS_ENABLED		(1 << 9)
> -#define   GUC_LOG_DEFAULT_DISABLED	(1 << 10)
> -#define   GUC_ADS_ADDR_SHIFT		11
> -#define   GUC_ADS_ADDR_MASK		0xfffff800
>   
> -#define GUC_CTL_RSRVD			9
> +#define GUC_CTL_ADS			5
> +#define   GUC_ADS_ADDR_SHIFT		1
> +#define   GUC_ADS_ADDR_MASK		(0xFFFFF << GUC_ADS_ADDR_SHIFT)
>   
>   #define GUC_CTL_MAX_DWORDS		(SOFT_SCRATCH_COUNT - 2) /* [1..14] */
>   
>
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c
index c0e8b359b23a..483c7019f817 100644
--- a/drivers/gpu/drm/i915/intel_guc.c
+++ b/drivers/gpu/drm/i915/intel_guc.c
@@ -243,14 +243,7 @@  void intel_guc_fini(struct intel_guc *guc)
 static u32 guc_ctl_debug_flags(struct intel_guc *guc)
 {
 	u32 level = intel_guc_log_get_level(&guc->log);
-	u32 flags;
-	u32 ads;
-
-	ads = intel_guc_ggtt_offset(guc, guc->ads_vma) >> PAGE_SHIFT;
-	flags = ads << GUC_ADS_ADDR_SHIFT | GUC_ADS_ENABLED;
-
-	if (!GUC_LOG_LEVEL_IS_ENABLED(level))
-		flags |= GUC_LOG_DEFAULT_DISABLED;
+	u32 flags = 0;
 
 	if (!GUC_LOG_LEVEL_IS_VERBOSE(level))
 		flags |= GUC_LOG_DISABLED;
@@ -265,11 +258,7 @@  static u32 guc_ctl_feature_flags(struct intel_guc *guc)
 {
 	u32 flags = 0;
 
-	flags |=  GUC_CTL_VCS2_ENABLED;
-
-	if (USES_GUC_SUBMISSION(guc_to_i915(guc)))
-		flags |= GUC_CTL_KERNEL_SUBMISSIONS;
-	else
+	if (!USES_GUC_SUBMISSION(guc_to_i915(guc)))
 		flags |= GUC_CTL_DISABLE_SCHEDULER;
 
 	return flags;
@@ -333,22 +322,21 @@  static u32 guc_ctl_log_params_flags(struct intel_guc *guc)
 	return flags;
 }
 
-static void guc_prepare_params(struct intel_guc *guc, u32 *params)
+static u32 guc_ctl_ads_flags(struct intel_guc *guc)
 {
-	/*
-	 * GuC ARAT increment is 10 ns. GuC default scheduler quantum is one
-	 * second. This ARAR is calculated by:
-	 * Scheduler-Quantum-in-ns / ARAT-increment-in-ns = 1000000000 / 10
-	 */
-	params[GUC_CTL_ARAT_HIGH] = 0;
-	params[GUC_CTL_ARAT_LOW] = 100000000;
+	u32 ads = intel_guc_ggtt_offset(guc, guc->ads_vma) >> PAGE_SHIFT;
+	u32 flags = ads << GUC_ADS_ADDR_SHIFT;
 
-	params[GUC_CTL_WA] |= GUC_CTL_WA_UK_BY_DRIVER;
+	return flags;
+}
 
+static void guc_prepare_params(struct intel_guc *guc, u32 *params)
+{
+	params[GUC_CTL_CTXINFO] = guc_ctl_ctxinfo_flags(guc);
+	params[GUC_CTL_LOG_PARAMS] = guc_ctl_log_params_flags(guc);
 	params[GUC_CTL_FEATURE] = guc_ctl_feature_flags(guc);
-	params[GUC_CTL_LOG_PARAMS]  = guc_ctl_log_params_flags(guc);
 	params[GUC_CTL_DEBUG] = guc_ctl_debug_flags(guc);
-	params[GUC_CTL_CTXINFO] = guc_ctl_ctxinfo_flags(guc);
+	params[GUC_CTL_ADS] = guc_ctl_ads_flags(guc);
 }
 
 static void guc_write_params(struct intel_guc *guc, const u32 *params)
diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h b/drivers/gpu/drm/i915/intel_guc_fwif.h
index 1cb4fad2d539..64b56da9775c 100644
--- a/drivers/gpu/drm/i915/intel_guc_fwif.h
+++ b/drivers/gpu/drm/i915/intel_guc_fwif.h
@@ -73,44 +73,28 @@ 
 #define GUC_STAGE_DESC_ATTR_PCH		BIT(6)
 #define GUC_STAGE_DESC_ATTR_TERMINATED	BIT(7)
 
-/* The guc control data is 10 DWORDs */
+/* New GuC control data */
 #define GUC_CTL_CTXINFO			0
 #define   GUC_CTL_CTXNUM_IN16_SHIFT	0
 #define   GUC_CTL_BASE_ADDR_SHIFT	12
 
-#define GUC_CTL_ARAT_HIGH		1
-#define GUC_CTL_ARAT_LOW		2
-
-#define GUC_CTL_DEVICE_INFO		3
-
-#define GUC_CTL_LOG_PARAMS		4
+#define GUC_CTL_LOG_PARAMS		1
 #define   GUC_LOG_VALID			(1 << 0)
 #define   GUC_LOG_NOTIFY_ON_HALF_FULL	(1 << 1)
 #define   GUC_LOG_ALLOC_IN_MEGABYTE	(1 << 3)
 #define   GUC_LOG_CRASH_SHIFT		4
-#define   GUC_LOG_CRASH_MASK		(0x1 << GUC_LOG_CRASH_SHIFT)
+#define   GUC_LOG_CRASH_MASK		(0x3 << GUC_LOG_CRASH_SHIFT)
 #define   GUC_LOG_DPC_SHIFT		6
 #define   GUC_LOG_DPC_MASK	        (0x7 << GUC_LOG_DPC_SHIFT)
 #define   GUC_LOG_ISR_SHIFT		9
 #define   GUC_LOG_ISR_MASK	        (0x7 << GUC_LOG_ISR_SHIFT)
 #define   GUC_LOG_BUF_ADDR_SHIFT	12
 
-#define GUC_CTL_PAGE_FAULT_CONTROL	5
-
-#define GUC_CTL_WA			6
-#define   GUC_CTL_WA_UK_BY_DRIVER	(1 << 3)
-
-#define GUC_CTL_FEATURE			7
-#define   GUC_CTL_VCS2_ENABLED		(1 << 0)
-#define   GUC_CTL_KERNEL_SUBMISSIONS	(1 << 1)
-#define   GUC_CTL_FEATURE2		(1 << 2)
-#define   GUC_CTL_POWER_GATING		(1 << 3)
-#define   GUC_CTL_DISABLE_SCHEDULER	(1 << 4)
-#define   GUC_CTL_PREEMPTION_LOG	(1 << 5)
-#define   GUC_CTL_ENABLE_SLPC		(1 << 7)
-#define   GUC_CTL_RESET_ON_PREMPT_FAILURE	(1 << 8)
+#define GUC_CTL_WA			2
+#define GUC_CTL_FEATURE			3
+#define   GUC_CTL_DISABLE_SCHEDULER	(1 << 14)
 
-#define GUC_CTL_DEBUG			8
+#define GUC_CTL_DEBUG			4
 #define   GUC_LOG_VERBOSITY_SHIFT	0
 #define   GUC_LOG_VERBOSITY_LOW		(0 << GUC_LOG_VERBOSITY_SHIFT)
 #define   GUC_LOG_VERBOSITY_MED		(1 << GUC_LOG_VERBOSITY_SHIFT)
@@ -123,13 +107,10 @@ 
 #define	  GUC_LOG_DESTINATION_MASK	(3 << 4)
 #define   GUC_LOG_DISABLED		(1 << 6)
 #define   GUC_PROFILE_ENABLED		(1 << 7)
-#define   GUC_WQ_TRACK_ENABLED		(1 << 8)
-#define   GUC_ADS_ENABLED		(1 << 9)
-#define   GUC_LOG_DEFAULT_DISABLED	(1 << 10)
-#define   GUC_ADS_ADDR_SHIFT		11
-#define   GUC_ADS_ADDR_MASK		0xfffff800
 
-#define GUC_CTL_RSRVD			9
+#define GUC_CTL_ADS			5
+#define   GUC_ADS_ADDR_SHIFT		1
+#define   GUC_ADS_ADDR_MASK		(0xFFFFF << GUC_ADS_ADDR_SHIFT)
 
 #define GUC_CTL_MAX_DWORDS		(SOFT_SCRATCH_COUNT - 2) /* [1..14] */