From patchwork Fri Apr 12 15:37:22 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mika Kuoppala X-Patchwork-Id: 10898561 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 6138C14DB for ; Fri, 12 Apr 2019 15:37:37 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 49C1228E6E for ; Fri, 12 Apr 2019 15:37:37 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 3E18E28E8B; Fri, 12 Apr 2019 15:37:37 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 73CF428E6E for ; Fri, 12 Apr 2019 15:37:35 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 17E0989A5E; Fri, 12 Apr 2019 15:37:34 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by gabe.freedesktop.org (Postfix) with ESMTPS id 0E11689A59 for ; Fri, 12 Apr 2019 15:37:33 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by fmsmga103.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 12 Apr 2019 08:37:32 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.60,341,1549958400"; d="scan'208";a="336556618" Received: from rosetta.fi.intel.com ([10.237.72.186]) by fmsmga006.fm.intel.com with ESMTP; 12 Apr 2019 08:37:31 -0700 Received: by rosetta.fi.intel.com (Postfix, from userid 1000) id 5B3FD8400FF; Fri, 12 Apr 2019 18:37:25 +0300 (EEST) From: Mika Kuoppala To: intel-gfx@lists.freedesktop.org Date: Fri, 12 Apr 2019 18:37:22 +0300 Message-Id: <20190412153723.31931-2-mika.kuoppala@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190412153723.31931-1-mika.kuoppala@linux.intel.com> References: <20190412153723.31931-1-mika.kuoppala@linux.intel.com> Subject: [Intel-gfx] [PATCH 2/3] drm/i915: Handle catastrophic error on engine reset X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP If cat error is set, we need to clear it by acking it. Further, if it is set, we must not do a normal request for reset. Bspec: 12567 Signed-off-by: Mika Kuoppala --- drivers/gpu/drm/i915/i915_reg.h | 6 +++-- drivers/gpu/drm/i915/i915_reset.c | 39 +++++++++++++++++++++---------- 2 files changed, 31 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 8ad2f0a03f28..c1c0f7ab03e9 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -2446,8 +2446,10 @@ enum i915_power_well_id { #define RING_HWS_PGA(base) _MMIO((base) + 0x80) #define RING_HWS_PGA_GEN6(base) _MMIO((base) + 0x2080) #define RING_RESET_CTL(base) _MMIO((base) + 0xd0) -#define RESET_CTL_REQUEST_RESET (1 << 0) -#define RESET_CTL_READY_TO_RESET (1 << 1) +#define RESET_CTL_CAT_ERROR REG_BIT(2) +#define RESET_CTL_READY_TO_RESET REG_BIT(1) +#define RESET_CTL_REQUEST_RESET REG_BIT(0) + #define RING_SEMA_WAIT_POLL(base) _MMIO((base) + 0x24c) #define HSW_GTT_CACHE_EN _MMIO(0x4024) diff --git a/drivers/gpu/drm/i915/i915_reset.c b/drivers/gpu/drm/i915/i915_reset.c index cde1a5309336..06310ee5a68a 100644 --- a/drivers/gpu/drm/i915/i915_reset.c +++ b/drivers/gpu/drm/i915/i915_reset.c @@ -490,25 +490,40 @@ static int gen11_reset_engines(struct drm_i915_private *i915, static int gen8_engine_reset_prepare(struct intel_engine_cs *engine) { struct intel_uncore *uncore = engine->uncore; - u32 ctl; + const i915_reg_t reg = RING_RESET_CTL(engine->mmio_base); + u32 ctl, ack = 0, mask = 0, request = 0; int ret; - ctl = intel_uncore_read_fw(uncore, RING_RESET_CTL(engine->mmio_base)); - if (ctl & RESET_CTL_READY_TO_RESET) + ctl = intel_uncore_read_fw(uncore, reg); + + if (INTEL_GEN(engine->i915) > 9 && (ctl & RESET_CTL_CAT_ERROR)) { + request |= RESET_CTL_CAT_ERROR; + mask |= RESET_CTL_CAT_ERROR; + + /* HAS#396813: Avoid reset request if cat error */ + goto skip_ready_req; + } + + if (!(ctl & RESET_CTL_READY_TO_RESET)) { + request |= RESET_CTL_REQUEST_RESET; + + mask |= RESET_CTL_READY_TO_RESET; + ack |= RESET_CTL_READY_TO_RESET; + } + + if (!request) return 0; - intel_uncore_write_fw(uncore, - RING_RESET_CTL(engine->mmio_base), - _MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET)); +skip_ready_req: + intel_uncore_write_fw(uncore, reg, _MASKED_BIT_ENABLE(request)); ret = __intel_wait_for_register_fw(uncore, - RING_RESET_CTL(engine->mmio_base), - RESET_CTL_READY_TO_RESET, - RESET_CTL_READY_TO_RESET, - 700, 0, - NULL); + reg, mask, ack, + 700, 0, NULL); if (ret) - DRM_ERROR("%s: reset request timeout\n", engine->name); + DRM_ERROR("%s: reset request 0x%08x timeout 0x%08x\n", + engine->name, request, + intel_uncore_read_fw(uncore, reg)); return ret; }