diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 06617a67002c..874668b5da57 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -651,6 +651,7 @@ struct intel_irq {
 	/* protects the irq masks */
 	spinlock_t lock;
 	bool rps_interrupts_enabled;
+	bool display_interrupts_enabled;
 	u32 pm_iir;
 };
 
@@ -1554,8 +1555,6 @@ struct drm_i915_private {
 
 	struct intel_irq irq;
 
-	bool display_irqs_enabled;
-
 	/* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
 	struct pm_qos_request pm_qos;
 
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 487ea27ea152..019472c98aac 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1912,7 +1912,7 @@ static void i9xx_pipestat_irq_ack(struct drm_i915_private *dev_priv,
 
 	spin_lock(&dev_priv->irq.lock);
 
-	if (!dev_priv->display_irqs_enabled) {
+	if (!dev_priv->irq.display_interrupts_enabled) {
 		spin_unlock(&dev_priv->irq.lock);
 		return;
 	}
@@ -3488,7 +3488,7 @@ static void valleyview_irq_reset(struct drm_device *dev)
 	gen5_gt_irq_reset(dev_priv);
 
 	spin_lock_irq(&dev_priv->irq.lock);
-	if (dev_priv->display_irqs_enabled)
+	if (dev_priv->irq.display_interrupts_enabled)
 		vlv_display_irq_reset(dev_priv);
 	spin_unlock_irq(&dev_priv->irq.lock);
 }
@@ -3634,7 +3634,7 @@ static void cherryview_irq_reset(struct drm_device *dev)
 	GEN3_IRQ_RESET(uncore, GEN8_PCU_);
 
 	spin_lock_irq(&dev_priv->irq.lock);
-	if (dev_priv->display_irqs_enabled)
+	if (dev_priv->irq.display_interrupts_enabled)
 		vlv_display_irq_reset(dev_priv);
 	spin_unlock_irq(&dev_priv->irq.lock);
 }
@@ -4010,10 +4010,10 @@ void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv)
 {
 	lockdep_assert_held(&dev_priv->irq.lock);
 
-	if (dev_priv->display_irqs_enabled)
+	if (dev_priv->irq.display_interrupts_enabled)
 		return;
 
-	dev_priv->display_irqs_enabled = true;
+	dev_priv->irq.display_interrupts_enabled = true;
 
 	if (intel_irqs_enabled(dev_priv)) {
 		vlv_display_irq_reset(dev_priv);
@@ -4025,10 +4025,10 @@ void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv)
 {
 	lockdep_assert_held(&dev_priv->irq.lock);
 
-	if (!dev_priv->display_irqs_enabled)
+	if (!dev_priv->irq.display_interrupts_enabled)
 		return;
 
-	dev_priv->display_irqs_enabled = false;
+	dev_priv->irq.display_interrupts_enabled = false;
 
 	if (intel_irqs_enabled(dev_priv))
 		vlv_display_irq_reset(dev_priv);
@@ -4042,7 +4042,7 @@ static int valleyview_irq_postinstall(struct drm_device *dev)
 	gen5_gt_irq_postinstall(dev);
 
 	spin_lock_irq(&dev_priv->irq.lock);
-	if (dev_priv->display_irqs_enabled)
+	if (dev_priv->irq.display_interrupts_enabled)
 		vlv_display_irq_postinstall(dev_priv);
 	spin_unlock_irq(&dev_priv->irq.lock);
 
@@ -4245,7 +4245,7 @@ static int cherryview_irq_postinstall(struct drm_device *dev)
 	gen8_gt_irq_postinstall(dev_priv);
 
 	spin_lock_irq(&dev_priv->irq.lock);
-	if (dev_priv->display_irqs_enabled)
+	if (dev_priv->irq.display_interrupts_enabled)
 		vlv_display_irq_postinstall(dev_priv);
 	spin_unlock_irq(&dev_priv->irq.lock);
 
@@ -4749,9 +4749,9 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
 	 * outside of the power domain. We defer setting up the display irqs
 	 * in this case to the runtime pm.
 	 */
-	dev_priv->display_irqs_enabled = true;
+	dev_priv->irq.display_interrupts_enabled = true;
 	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
-		dev_priv->display_irqs_enabled = false;
+		dev_priv->irq.display_interrupts_enabled = false;
 
 	dev_priv->hotplug.hpd_storm_threshold = HPD_STORM_DEFAULT_THRESHOLD;
 	/* If we have MST support, we want to avoid doing short HPD IRQ storm
diff --git a/drivers/gpu/drm/i915/intel_hotplug.c b/drivers/gpu/drm/i915/intel_hotplug.c
index 8260e81f88e7..89ee666eb78c 100644
--- a/drivers/gpu/drm/i915/intel_hotplug.c
+++ b/drivers/gpu/drm/i915/intel_hotplug.c
@@ -258,7 +258,8 @@ static void intel_hpd_irq_storm_reenable_work(struct work_struct *work)
 		}
 		drm_connector_list_iter_end(&conn_iter);
 	}
-	if (dev_priv->display_irqs_enabled && dev_priv->display.hpd_irq_setup)
+	if (dev_priv->irq.display_interrupts_enabled &&
+	    dev_priv->display.hpd_irq_setup)
 		dev_priv->display.hpd_irq_setup(dev_priv);
 	spin_unlock_irq(&dev_priv->irq.lock);
 
@@ -502,7 +503,7 @@ void intel_hpd_irq_handler(struct drm_i915_private *dev_priv,
 	 * Disable any IRQs that storms were detected on. Polling enablement
 	 * happens later in our hotplug work.
 	 */
-	if (storm_detected && dev_priv->display_irqs_enabled)
+	if (storm_detected && dev_priv->irq.display_interrupts_enabled)
 		dev_priv->display.hpd_irq_setup(dev_priv);
 	spin_unlock(&dev_priv->irq.lock);
 
@@ -548,9 +549,10 @@ void intel_hpd_init(struct drm_i915_private *dev_priv)
 	 * Interrupt setup is already guaranteed to be single-threaded, this is
 	 * just to make the assert_spin_locked checks happy.
 	 */
-	if (dev_priv->display_irqs_enabled && dev_priv->display.hpd_irq_setup) {
+	if (dev_priv->irq.display_interrupts_enabled &&
+	    dev_priv->display.hpd_irq_setup) {
 		spin_lock_irq(&dev_priv->irq.lock);
-		if (dev_priv->display_irqs_enabled)
+		if (dev_priv->irq.display_interrupts_enabled)
 			dev_priv->display.hpd_irq_setup(dev_priv);
 		spin_unlock_irq(&dev_priv->irq.lock);
 	}
