From patchwork Fri Jun 14 00:28:38 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Fosha, Robert M" X-Patchwork-Id: 10993895 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id F166B13AF for ; Fri, 14 Jun 2019 00:33:40 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E28EC26E78 for ; Fri, 14 Jun 2019 00:33:40 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id D7257277D9; Fri, 14 Jun 2019 00:33:40 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 7DF8926E78 for ; Fri, 14 Jun 2019 00:33:40 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 1410E892F8; Fri, 14 Jun 2019 00:33:40 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTPS id BEB47892F8 for ; Fri, 14 Jun 2019 00:33:38 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 13 Jun 2019 17:33:38 -0700 X-ExtLoop1: 1 Received: from rmfosha-dev-1.fm.intel.com ([10.19.83.123]) by fmsmga008.fm.intel.com with ESMTP; 13 Jun 2019 17:33:38 -0700 From: "Robert M. Fosha" To: intel-gfx@lists.freedesktop.org Date: Thu, 13 Jun 2019 17:28:38 -0700 Message-Id: <20190614002838.3072-5-robert.m.fosha@intel.com> X-Mailer: git-send-email 2.21.0.5.gaeb582a983 In-Reply-To: <20190614002838.3072-1-robert.m.fosha@intel.com> References: <20190614002838.3072-1-robert.m.fosha@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 4/4] drm/i915: Add whitelist workarounds for ICL X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP From: John Harrison Updated whitelist table for ICL. Signed-off-by: John Harrison Signed-off-by: Robert M. Fosha Cc: Tvrtko Ursulin Cc: Chris Wilson Reviewed-by: Tvrtko Ursulin --- drivers/gpu/drm/i915/gt/intel_workarounds.c | 87 +++++++++++++++++++-- 1 file changed, 79 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index 60bd515edaf1..aa99fb3ffbcb 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -1146,17 +1146,88 @@ static void icl_whitelist_build(struct intel_engine_cs *engine) { struct i915_wa_list *w = &engine->whitelist; - if (engine->class != RENDER_CLASS) - return; + switch (engine->class) { + case RENDER_CLASS: + /* WaSendPushConstantsFromMMIO:icl */ + whitelist_reg_ext(w, COMMON_SLICE_CHICKEN2, + RING_FORCE_TO_NONPRIV_RW); - /* WaAllowUMDToModifyHalfSliceChicken7:icl */ - whitelist_reg(w, GEN9_HALF_SLICE_CHICKEN7); + /* WaAllowUMDToModifyHalfSliceChicken7:icl */ + whitelist_reg_ext(w, GEN9_HALF_SLICE_CHICKEN7, + RING_FORCE_TO_NONPRIV_RW); - /* WaAllowUMDToModifySamplerMode:icl */ - whitelist_reg(w, GEN10_SAMPLER_MODE); + /* WaAllowUMDToModifySamplerMode:icl */ + whitelist_reg_ext(w, GEN10_SAMPLER_MODE, + RING_FORCE_TO_NONPRIV_RW); - /* WaEnableStateCacheRedirectToCS:icl */ - whitelist_reg(w, GEN9_SLICE_COMMON_ECO_CHICKEN1); + /* WaEnableStateCacheRedirectToCS:icl */ + whitelist_reg_ext(w, GEN9_SLICE_COMMON_ECO_CHICKEN1, + RING_FORCE_TO_NONPRIV_RW); + + /* WaAllowUMDToModifyHalfSliceChicken2:icl */ + whitelist_reg_ext(w, HALF_SLICE_CHICKEN2, + RING_FORCE_TO_NONPRIV_RW); + + /* WaDisableMidObjectPreemptioninUMD:icl */ + whitelist_reg_ext(w, GEN8_CS_CHICKEN1, + RING_FORCE_TO_NONPRIV_RW); + + /* FtrSSEUPowerGatingControlByUMD:icl */ + whitelist_reg_ext(w, _MMIO(0x20C8), RING_FORCE_TO_NONPRIV_RW); + + /* WaUseOaReportTriggersForQuery:icl */ + whitelist_reg_ext(w, OAREPORTTRIG2, RING_FORCE_TO_NONPRIV_RW); + + /* WaAllowUmdWriteTRTTRootTable:icl */ + whitelist_reg_ext(w, _MMIO(0x4DE0), RING_FORCE_TO_NONPRIV_RW); + whitelist_reg_ext(w, _MMIO(0x4DE4), RING_FORCE_TO_NONPRIV_RW); + + /* CL_PRIMITIVE_COUNT/PS_INVOCATIONS_COUNT */ + whitelist_reg_ext(w, CL_PRIMITIVES_COUNT, + RING_FORCE_TO_NONPRIV_RD | + RING_FORCE_TO_NONPRIV_RANGE_4); + + /* PS_DEPTH_COUNT */ + whitelist_reg_ext(w, PS_DEPTH_COUNT, RING_FORCE_TO_NONPRIV_RD | + RING_FORCE_TO_NONPRIV_RANGE_4); + + /* EUMETRICS_EVENT_0 -> _5 */ + whitelist_reg_ext(w, _MMIO(0xD8C), RING_FORCE_TO_NONPRIV_RD); + whitelist_reg_ext(w, _MMIO(0xD90), RING_FORCE_TO_NONPRIV_RD | + RING_FORCE_TO_NONPRIV_RANGE_4); + whitelist_reg_ext(w, _MMIO(0xDA0), RING_FORCE_TO_NONPRIV_RD); + + /* SRD_PERF_COUNTER */ + whitelist_reg_ext(w, _MMIO(0x64844), RING_FORCE_TO_NONPRIV_RD); + + /* WaAllowUMDAccesstoOARegisters:icl */ + whitelist_reg_ext(w, _MMIO(0x28A0), RING_FORCE_TO_NONPRIV_RW); + whitelist_reg_ext(w, OAREPORTTRIG6, RING_FORCE_TO_NONPRIV_RW); + break; + case VIDEO_DECODE_CLASS: + /* hucStatusRegOffset */ + whitelist_reg_ext(w, _MMIO(0x2000 + engine->mmio_base), + RING_FORCE_TO_NONPRIV_RD); + /* hucUKernelHdrInfoRegOffset */ + whitelist_reg_ext(w, _MMIO(0x2014 + engine->mmio_base), + RING_FORCE_TO_NONPRIV_RD); + /* hucStatus2RegOffset */ + whitelist_reg_ext(w, _MMIO(0x23B0 + engine->mmio_base), + RING_FORCE_TO_NONPRIV_RD); + + /* fall through */ + case VIDEO_ENHANCEMENT_CLASS: + /* WATCHDOG_COUNT_CONTROL */ + whitelist_reg_ext(w, _MMIO(0x178 + engine->mmio_base), + RING_FORCE_TO_NONPRIV_RD); + + /* WATCHDOG_COUNT_THRESHOLD */ + whitelist_reg_ext(w, _MMIO(0x17C + engine->mmio_base), + RING_FORCE_TO_NONPRIV_RD); + break; + default: + break; + } } void intel_engine_init_whitelist(struct intel_engine_cs *engine)