| Message ID | 20190614164350.30415-8-mika.kuoppala@linux.intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [01/10] drm/i915/gtt: No need to zero the table for page dirs | expand |
Quoting Mika Kuoppala (2019-06-14 17:43:48) > Swapping a pd entry is same across the page directories, if > we succeed we need to increment the count and write the phys page > entry. Make a common function for it. > > v2: inline (Chris) > > Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> > --- > drivers/gpu/drm/i915/i915_gem_gtt.c | 42 +++++++++++++++++++---------- > 1 file changed, 28 insertions(+), 14 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c > index 8baceb9f64c5..0fffa0608ea5 100644 > --- a/drivers/gpu/drm/i915/i915_gem_gtt.c > +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c > @@ -754,6 +754,28 @@ static void __set_pd_entry(struct i915_page_directory * const pd, > gen8_pde_encode(px_dma(to), I915_CACHE_LLC)); \ > }) > > +static inline void * > +__swap_pd_entry(struct i915_page_directory * const pd, > + const unsigned short pde, These can be the struct px_dma base type (or whatever that was called) > + void * const old_val, > + void * const new_val, > + const dma_addr_t daddr, > + u64 (*encode)(const dma_addr_t, const enum i915_cache_level)) > +{ > + void * const old = cmpxchg(&pd->entry[pde], old_val, new_val); > + > + if (likely(old == old_val)) { > + atomic_inc(&pd->used); > + if (likely(pd_has_phys_page(pd))) > + __set_pd_entry(pd, pde, encode(daddr, I915_CACHE_LLC)); and then s/daddr/px_dma(to))/ ? > + } > + > + return old; > +} > + > +#define swap_pd_entry(pd, pde, old, to) \ > + __swap_pd_entry((pd), (pde), (old), (to), px_dma(to), gen8_pde_encode) > + > /* > * PDE TLBs are a pain to invalidate on GEN8+. When we modify > * the page table structures, we mark them dirty so that > @@ -1328,11 +1350,8 @@ static int gen8_ppgtt_alloc_pd(struct i915_address_space *vm, > if (count < GEN8_PTES || intel_vgpu_active(vm->i915)) > gen8_initialize_pt(vm, pt); > > - old = cmpxchg(&pd->entry[pde], vm->scratch_pt, pt); > - if (old == vm->scratch_pt) { > - set_pd_entry(pd, pde, pt); > - atomic_inc(&pd->used); > - } else { > + old = swap_pd_entry(pd, pde, vm->scratch_pt, pt); > + if (unlikely(old != vm->scratch_pt)) { > free_pt(vm, pt); > pt = old; > } > @@ -1373,11 +1392,8 @@ static int gen8_ppgtt_alloc_pdp(struct i915_address_space *vm, > > init_pd(vm, pd, vm->scratch_pt); > > - old = cmpxchg(&pdp->entry[pdpe], vm->scratch_pd, pd); > - if (old == vm->scratch_pd) { > - set_pd_entry(pdp, pdpe, pd); > - atomic_inc(&pdp->used); > - } else { > + old = swap_pd_entry(pdp, pdpe, vm->scratch_pd, pd); > + if (unlikely(old != vm->scratch_pd)) { > free_pd(vm, pd); > pd = old; > } > @@ -1442,10 +1458,8 @@ static int gen8_ppgtt_alloc_4lvl(struct i915_address_space *vm, > > init_pd(vm, pdp, vm->scratch_pd); > > - old = cmpxchg(&pml4->entry[pml4e], vm->scratch_pdp, pdp); > - if (old == vm->scratch_pdp) { > - set_pd_entry(pml4, pml4e, pdp); > - } else { > + old = swap_pd_entry(pml4, pml4e, vm->scratch_pdp, pdp); > + if (unlikely(old != vm->scratch_pdp)) { > free_pd(vm, pdp); > pdp = old; Otherwise, the only difference between these stanzas is now vm->scratch[lvl] :) Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> -Chris
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index 8baceb9f64c5..0fffa0608ea5 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c @@ -754,6 +754,28 @@ static void __set_pd_entry(struct i915_page_directory * const pd, gen8_pde_encode(px_dma(to), I915_CACHE_LLC)); \ }) +static inline void * +__swap_pd_entry(struct i915_page_directory * const pd, + const unsigned short pde, + void * const old_val, + void * const new_val, + const dma_addr_t daddr, + u64 (*encode)(const dma_addr_t, const enum i915_cache_level)) +{ + void * const old = cmpxchg(&pd->entry[pde], old_val, new_val); + + if (likely(old == old_val)) { + atomic_inc(&pd->used); + if (likely(pd_has_phys_page(pd))) + __set_pd_entry(pd, pde, encode(daddr, I915_CACHE_LLC)); + } + + return old; +} + +#define swap_pd_entry(pd, pde, old, to) \ + __swap_pd_entry((pd), (pde), (old), (to), px_dma(to), gen8_pde_encode) + /* * PDE TLBs are a pain to invalidate on GEN8+. When we modify * the page table structures, we mark them dirty so that @@ -1328,11 +1350,8 @@ static int gen8_ppgtt_alloc_pd(struct i915_address_space *vm, if (count < GEN8_PTES || intel_vgpu_active(vm->i915)) gen8_initialize_pt(vm, pt); - old = cmpxchg(&pd->entry[pde], vm->scratch_pt, pt); - if (old == vm->scratch_pt) { - set_pd_entry(pd, pde, pt); - atomic_inc(&pd->used); - } else { + old = swap_pd_entry(pd, pde, vm->scratch_pt, pt); + if (unlikely(old != vm->scratch_pt)) { free_pt(vm, pt); pt = old; } @@ -1373,11 +1392,8 @@ static int gen8_ppgtt_alloc_pdp(struct i915_address_space *vm, init_pd(vm, pd, vm->scratch_pt); - old = cmpxchg(&pdp->entry[pdpe], vm->scratch_pd, pd); - if (old == vm->scratch_pd) { - set_pd_entry(pdp, pdpe, pd); - atomic_inc(&pdp->used); - } else { + old = swap_pd_entry(pdp, pdpe, vm->scratch_pd, pd); + if (unlikely(old != vm->scratch_pd)) { free_pd(vm, pd); pd = old; } @@ -1442,10 +1458,8 @@ static int gen8_ppgtt_alloc_4lvl(struct i915_address_space *vm, init_pd(vm, pdp, vm->scratch_pd); - old = cmpxchg(&pml4->entry[pml4e], vm->scratch_pdp, pdp); - if (old == vm->scratch_pdp) { - set_pd_entry(pml4, pml4e, pdp); - } else { + old = swap_pd_entry(pml4, pml4e, vm->scratch_pdp, pdp); + if (unlikely(old != vm->scratch_pdp)) { free_pd(vm, pdp); pdp = old; }
Swapping a pd entry is same across the page directories, if we succeed we need to increment the count and write the phys page entry. Make a common function for it. v2: inline (Chris) Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> --- drivers/gpu/drm/i915/i915_gem_gtt.c | 42 +++++++++++++++++++---------- 1 file changed, 28 insertions(+), 14 deletions(-)