diff mbox series

[2/2] drm/i915/icl: whitelist PS_(DEPTH|INVOCATION)_COUNT

Message ID 20190620071546.19852-3-lionel.g.landwerlin@intel.com (mailing list archive)
State New, archived
Headers show
Series drm/i915: CTS fixes | expand

Commit Message

Lionel Landwerlin June 20, 2019, 7:15 a.m. UTC 
The same tests failing on CFL+ platforms are also failing on ICL.
Documentation doesn't list the
WaAllowPMDepthAndInvocationCountAccessFromUMD workaround for ICL but
applying it fixes the same tests as CFL.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 6 ++++++
 1 file changed, 6 insertions(+)
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 90df58ed1486..84a679606971 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1092,6 +1092,12 @@  static void icl_whitelist_build(struct i915_wa_list *w)
 
 	/* WaEnableStateCacheRedirectToCS:icl */
 	whitelist_reg(w, GEN9_SLICE_COMMON_ECO_CHICKEN1);
+
+	/* WaAllowPMDepthAndInvocationCountAccessFromUMD:icl */
+	whitelist_reg(w, PS_DEPTH_COUNT);
+	whitelist_reg(w, PS_DEPTH_COUNT_UDW);
+	whitelist_reg(w, PS_INVOCATION_COUNT);
+	whitelist_reg(w, PS_INVOCATION_COUNT_UDW);
 }
 
 void intel_engine_init_whitelist(struct intel_engine_cs *engine)