diff mbox series

[v4,2/3] drm/i915: whitelist PS_(DEPTH|INVOCATION)_COUNT

Message ID 20190625135503.4262-3-lionel.g.landwerlin@intel.com (mailing list archive)
State New, archived
Headers show
Series drm/i915: CTS fixes | expand

Commit Message

Lionel Landwerlin June 25, 2019, 1:55 p.m. UTC 
CFL:C0+ changed the status of those registers which are now
blacklisted by default.

This is breaking a number of CTS tests on GL & Vulkan :

  KHR-GL45.pipeline_statistics_query_tests_ARB.functional_fragment_shader_invocations (GL)

  dEQP-VK.query_pool.statistics_query.fragment_shader_invocations.* (Vulkan)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 993804d09517..da7d48ac4ee7 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1092,10 +1092,18 @@  static void glk_whitelist_build(struct intel_engine_cs *engine)
 
 static void cfl_whitelist_build(struct intel_engine_cs *engine)
 {
+	struct i915_wa_list *w = &engine->whitelist;
+
 	if (engine->class != RENDER_CLASS)
 		return;
 
-	gen9_whitelist_build(&engine->whitelist);
+	gen9_whitelist_build(w);
+
+	/* WaAllowPMDepthAndInvocationCountAccessFromUMD:cfl,whl,cml,aml */
+	whitelist_reg_ext(w, PS_DEPTH_COUNT, RING_FORCE_TO_NONPRIV_RD);
+	whitelist_reg_ext(w, PS_DEPTH_COUNT_UDW, RING_FORCE_TO_NONPRIV_RD);
+	whitelist_reg_ext(w, PS_INVOCATION_COUNT, RING_FORCE_TO_NONPRIV_RD);
+	whitelist_reg_ext(w, PS_INVOCATION_COUNT_UDW, RING_FORCE_TO_NONPRIV_RD);
 }
 
 static void cnl_whitelist_build(struct intel_engine_cs *engine)