diff mbox series

[v5,3/3] drm/i915/icl: whitelist PS_(DEPTH|INVOCATION)_COUNT

Message ID 20190625182257.22075-4-lionel.g.landwerlin@intel.com (mailing list archive)
State New, archived
Headers show
Series drm/i915: CTS fixes | expand

Commit Message

Lionel Landwerlin June 25, 2019, 6:22 p.m. UTC 
The same tests failing on CFL+ platforms are also failing on ICL.
Documentation doesn't list the
WaAllowPMDepthAndInvocationCountAccessFromUMD workaround for ICL but
applying it fixes the same tests as CFL.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 6 ++++++
 1 file changed, 6 insertions(+)
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index da7d48ac4ee7..9a19980cceb5 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1131,6 +1131,12 @@  static void icl_whitelist_build(struct intel_engine_cs *engine)
 
 		/* WaEnableStateCacheRedirectToCS:icl */
 		whitelist_reg(w, GEN9_SLICE_COMMON_ECO_CHICKEN1);
+
+		/* WaAllowPMDepthAndInvocationCountAccessFromUMD:icl */
+		whitelist_reg_ext(w, PS_DEPTH_COUNT, RING_FORCE_TO_NONPRIV_RD);
+		whitelist_reg_ext(w, PS_DEPTH_COUNT_UDW, RING_FORCE_TO_NONPRIV_RD);
+		whitelist_reg_ext(w, PS_INVOCATION_COUNT, RING_FORCE_TO_NONPRIV_RD);
+		whitelist_reg_ext(w, PS_INVOCATION_COUNT_UDW, RING_FORCE_TO_NONPRIV_RD);
 		break;
 
 	case VIDEO_DECODE_CLASS: