From patchwork Fri Jun 28 13:07:51 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Gupta, Anshuman" X-Patchwork-Id: 11022441 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B9CE376 for ; Fri, 28 Jun 2019 13:12:57 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id AC62328763 for ; Fri, 28 Jun 2019 13:12:57 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id A0C79287AA; Fri, 28 Jun 2019 13:12:57 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 48EE728763 for ; Fri, 28 Jun 2019 13:12:57 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id BD8A66E926; Fri, 28 Jun 2019 13:12:56 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTPS id D97A46E926 for ; Fri, 28 Jun 2019 13:12:52 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 28 Jun 2019 06:12:52 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.63,427,1557212400"; d="scan'208";a="314131489" Received: from genxfsim-desktop.iind.intel.com ([10.223.74.120]) by orsmga004.jf.intel.com with ESMTP; 28 Jun 2019 06:12:50 -0700 From: Anshuman Gupta To: intel-gfx@lists.freedesktop.org Date: Fri, 28 Jun 2019 18:37:51 +0530 Message-Id: <20190628130754.9527-8-anshuman.gupta@intel.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190628130754.9527-1-anshuman.gupta@intel.com> References: <20190628130754.9527-1-anshuman.gupta@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 07/10] drm/i915/tgl:DC3CO PSR2 helper. X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jani.nikula@intel.com Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP This patch adds dc3co helper function to enable/disable psr2 deep sleep. This patch make sure DC3CO disallowed before PSR2 exit, it does that essentially by putting a reference to POWER_DOMAIN_VIDEO before PSR2 exit. Cc: jani.nikula@intel.com Cc: imre.deak@intel.com Cc: jose.souza@intel.com Cc: animesh.manna@intel.com Signed-off-by: Anshuman Gupta --- drivers/gpu/drm/i915/intel_psr.c | 55 ++++++++++++++++++++++++++++++++ drivers/gpu/drm/i915/intel_psr.h | 2 ++ 2 files changed, 57 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c index 963663ba0edf..1c0cbfd50ad4 100644 --- a/drivers/gpu/drm/i915/intel_psr.c +++ b/drivers/gpu/drm/i915/intel_psr.c @@ -542,6 +542,60 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp) I915_WRITE(EDP_PSR2_CTL, val); } +void tgl_psr2_deep_sleep_disable(struct drm_i915_private *dev_priv) +{ + u32 val; + int idle_frames = 0; + + idle_frames <<= EDP_PSR2_IDLE_FRAME_SHIFT; + /* + * PSR registers are moved to each transcoder, it requires + * https://patchwork.freedesktop.org/series/62416/ series + * to be merged in order to use new PSR macro, as of now + * using old PSR register macro to avoid compilation error. + * similar logic on other places using the PSR2_CTL reg. + */ + //val = I915_READ(EDP_PSR2_CTL(dev_priv->psr.transcoder)); + val = I915_READ(EDP_PSR2_CTL); + val &= ~EDP_PSR2_IDLE_FRAME_MASK; + val |= idle_frames; + //I915_WRITE(EDP_PSR2_CTL(dev_priv->psr.transcoder), val); + I915_WRITE(EDP_PSR2_CTL, val); +} + +void tgl_psr2_deep_sleep_enable(struct drm_i915_private *dev_priv) +{ + u32 val; + int idle_frames; + + /* + * Let's use 6 as the minimum to cover all known cases including the + * off-by-one issue that HW has in some cases. + */ + idle_frames = max(6, dev_priv->vbt.psr.idle_frames); + idle_frames = max(idle_frames, dev_priv->psr.sink_sync_latency + 1); + idle_frames <<= EDP_PSR2_IDLE_FRAME_SHIFT; + //val = I915_READ(EDP_PSR2_CTL(dev_priv->psr.transcoder)); + val = I915_READ(EDP_PSR2_CTL); + val &= ~EDP_PSR2_IDLE_FRAME_MASK; + val |= idle_frames; + //I915_WRITE(EDP_PSR2_CTL(dev_priv->psr.transcoder), val); + I915_WRITE(EDP_PSR2_CTL, val); +} + +void tgl_disallow_dc3co_on_psr2_exit(struct drm_i915_private *dev_priv) +{ + intel_wakeref_t wakeref __maybe_unused; + + /* Before PSR2 exit disallow dc3co*/ + mutex_lock(&dev_priv->csr.dc5_mutex); + wakeref = fetch_and_zero(&dev_priv->csr.dc5_wakeref); + if (wakeref) + intel_display_power_put(dev_priv, POWER_DOMAIN_VIDEO, + dev_priv->csr.dc5_wakeref); + mutex_unlock(&dev_priv->csr.dc5_mutex); +} + static bool intel_psr2_config_valid(struct intel_dp *intel_dp, struct intel_crtc_state *crtc_state) { @@ -798,6 +852,7 @@ static void intel_psr_exit(struct drm_i915_private *dev_priv) } if (dev_priv->psr.psr2_enabled) { + tgl_disallow_dc3co_on_psr2_exit(dev_priv); val = I915_READ(EDP_PSR2_CTL); WARN_ON(!(val & EDP_PSR2_ENABLE)); I915_WRITE(EDP_PSR2_CTL, val & ~EDP_PSR2_ENABLE); diff --git a/drivers/gpu/drm/i915/intel_psr.h b/drivers/gpu/drm/i915/intel_psr.h index dc818826f36d..6fb4c385489c 100644 --- a/drivers/gpu/drm/i915/intel_psr.h +++ b/drivers/gpu/drm/i915/intel_psr.h @@ -36,5 +36,7 @@ void intel_psr_short_pulse(struct intel_dp *intel_dp); int intel_psr_wait_for_idle(const struct intel_crtc_state *new_crtc_state, u32 *out_value); bool intel_psr_enabled(struct intel_dp *intel_dp); +void tgl_psr2_deep_sleep_disable(struct drm_i915_private *dev_priv); +void tgl_psr2_deep_sleep_enable(struct drm_i915_private *dev_priv); #endif /* __INTEL_PSR_H__ */