@@ -1880,6 +1880,8 @@ struct drm_i915_private {
/* Mutex to protect the above hdcp component related values. */
struct mutex hdcp_comp_mutex;
+ struct intel_dsb *dsb;
+
/*
* NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
* will be rejected. Instead look for a better place.
@@ -2716,7 +2718,9 @@ extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
intel_uncore_##op__(&(dev_priv__)->uncore, __VA_ARGS__)
#define I915_READ(reg__) __I915_REG_OP(read, dev_priv, (reg__))
-#define I915_WRITE(reg__, val__) __I915_REG_OP(write, dev_priv, (reg__), (val__))
+#define I915_WRITE(reg__, val__) \
+ (reg__.cap) ? intel_dsb_reg_write(dev_priv->dsb, (reg__), (val__)) : \
+ __I915_REG_OP(write, dev_priv, (reg__), (val__))
#define POSTING_READ(reg__) __I915_REG_OP(posting_read, dev_priv, (reg__))
@@ -122,7 +122,7 @@ void intel_dsb_reg_write(struct intel_dsb *dsb, i915_reg_t reg, u32 val)
u32 *buf = dsb->cmd_buf;
if (!buf) {
- I915_WRITE(reg, val);
+ intel_uncore_write(&(dev_priv)->uncore, reg, val);
return;
}
Existing mmio-reg-write need intel_uncore handle which is part of dev_priv structure and the same design is followed by adding dsb handle in dev_priv for programming registers through DSB. I915_WRITE is modified to check for register capability and call dsb-reg-write based on its capability. No changes in I915_READ definition as DSB do not have support to read any register. Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Jani Nikula <jani.nikula@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Animesh Manna <animesh.manna@intel.com> --- drivers/gpu/drm/i915/i915_drv.h | 6 +++++- drivers/gpu/drm/i915/intel_dsb.c | 2 +- 2 files changed, 6 insertions(+), 2 deletions(-)