| Message ID | 20190702041850.4293-5-vandita.kulkarni@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Support mipi dsi video mode on TGL | expand |
>-----Original Message----- >From: Kulkarni, Vandita >Sent: Tuesday, July 2, 2019 9:49 AM >To: intel-gfx@lists.freedesktop.org >Cc: ville.syrjala@linux.intel.com; Nikula, Jani <jani.nikula@intel.com>; Shankar, Uma ><uma.shankar@intel.com>; Kulkarni, Vandita <vandita.kulkarni@intel.com> >Subject: [PATCH 4/4] drm/i915/tgl/dsi: Gate the ddi clocks after pll mapping > >No need to keep it on till IO enabling. Minor nit: You can replace "it" by "ddi clock". Also add that when (at what stage) they get enabled to give a relative picture. With this fixed. Reviewed-by: Uma Shankar <uma.shankar@intel.com> >Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com> >--- > drivers/gpu/drm/i915/display/icl_dsi.c | 11 +++++++++-- > 1 file changed, 9 insertions(+), 2 deletions(-) > >diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c >b/drivers/gpu/drm/i915/display/icl_dsi.c >index d1c50a4186f0..99ce8c708353 100644 >--- a/drivers/gpu/drm/i915/display/icl_dsi.c >+++ b/drivers/gpu/drm/i915/display/icl_dsi.c >@@ -609,8 +609,12 @@ static void gen11_dsi_map_pll(struct intel_encoder >*encoder, > I915_WRITE(DPCLKA_CFGCR0_ICL, val); > > for_each_dsi_port(port, intel_dsi->ports) { >- val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port); >+ if (INTEL_GEN(dev_priv) >= 12) >+ val |= DPCLKA_CFGCR0_DDI_CLK_OFF(port); >+ else >+ val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port); > } >+ > I915_WRITE(DPCLKA_CFGCR0_ICL, val); > > POSTING_READ(DPCLKA_CFGCR0_ICL); >@@ -955,6 +959,8 @@ static void > gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder, > const struct intel_crtc_state *pipe_config) { >+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); >+ > /* step 4a: power up all lanes of the DDI used by DSI */ > gen11_dsi_power_up_lanes(encoder); > >@@ -977,7 +983,8 @@ gen11_dsi_enable_port_and_phy(struct intel_encoder >*encoder, > gen11_dsi_configure_transcoder(encoder, pipe_config); > > /* Step 4l: Gate DDI clocks */ >- gen11_dsi_gate_clocks(encoder); >+ if (IS_GEN(dev_priv, 11)) >+ gen11_dsi_gate_clocks(encoder); > } > > static void gen11_dsi_powerup_panel(struct intel_encoder *encoder) >-- >2.21.0.5.gaeb582a
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c index d1c50a4186f0..99ce8c708353 100644 --- a/drivers/gpu/drm/i915/display/icl_dsi.c +++ b/drivers/gpu/drm/i915/display/icl_dsi.c @@ -609,8 +609,12 @@ static void gen11_dsi_map_pll(struct intel_encoder *encoder, I915_WRITE(DPCLKA_CFGCR0_ICL, val); for_each_dsi_port(port, intel_dsi->ports) { - val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port); + if (INTEL_GEN(dev_priv) >= 12) + val |= DPCLKA_CFGCR0_DDI_CLK_OFF(port); + else + val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port); } + I915_WRITE(DPCLKA_CFGCR0_ICL, val); POSTING_READ(DPCLKA_CFGCR0_ICL); @@ -955,6 +959,8 @@ static void gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder, const struct intel_crtc_state *pipe_config) { + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + /* step 4a: power up all lanes of the DDI used by DSI */ gen11_dsi_power_up_lanes(encoder); @@ -977,7 +983,8 @@ gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder, gen11_dsi_configure_transcoder(encoder, pipe_config); /* Step 4l: Gate DDI clocks */ - gen11_dsi_gate_clocks(encoder); + if (IS_GEN(dev_priv, 11)) + gen11_dsi_gate_clocks(encoder); } static void gen11_dsi_powerup_panel(struct intel_encoder *encoder)
No need to keep it on till IO enabling. Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com> --- drivers/gpu/drm/i915/display/icl_dsi.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-)