| Message ID | 20190710141257.1062-1-stanislav.lisovskiy@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/i915: Fix wrong escape clock divisor init for GLK | expand |
Op 10-07-2019 om 16:12 schreef Stanislav Lisovskiy: > According to Bspec clock divisor registers in GeminiLake > should be initialized by shifting 1(<<) to amount of correspondent > divisor. While i915 was writing all this time that value as is. > > Surprisingly that it by accident worked, until we met some issues > with Microtech Etab. > > Signed-off-by: Stanislav.Lisovskiy@intel.com > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108826 > --- > drivers/gpu/drm/i915/display/vlv_dsi_pll.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/vlv_dsi_pll.c b/drivers/gpu/drm/i915/display/vlv_dsi_pll.c > index 99cc3e2e9c2c..f016a776a39e 100644 > --- a/drivers/gpu/drm/i915/display/vlv_dsi_pll.c > +++ b/drivers/gpu/drm/i915/display/vlv_dsi_pll.c > @@ -396,8 +396,8 @@ static void glk_dsi_program_esc_clock(struct drm_device *dev, > else > txesc2_div = 10; > > - I915_WRITE(MIPIO_TXESC_CLK_DIV1, txesc1_div & GLK_TX_ESC_CLK_DIV1_MASK); > - I915_WRITE(MIPIO_TXESC_CLK_DIV2, txesc2_div & GLK_TX_ESC_CLK_DIV2_MASK); > + I915_WRITE(MIPIO_TXESC_CLK_DIV1, (1 << (txesc1_div - 1)) & GLK_TX_ESC_CLK_DIV1_MASK); > + I915_WRITE(MIPIO_TXESC_CLK_DIV2, (1 << (txesc2_div - 1)) & GLK_TX_ESC_CLK_DIV2_MASK); > } > > /* Program BXT Mipi clocks and dividers */ Missing a fixes tag? find the original commit that introduced this, then run dim fixes $commitid. Cheers, Maarten
> -----Original Message----- > From: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> > Sent: Wednesday, July 10, 2019 8:04 PM > To: Lisovskiy, Stanislav <stanislav.lisovskiy@intel.com>; intel- > gfx@lists.freedesktop.org > Cc: Peres, Martin <martin.peres@intel.com>; ville.syrjala@linux.intel.com; > Saarinen, Jani <jani.saarinen@intel.com>; Nikula, Jani <jani.nikula@intel.com>; > Kulkarni, Vandita <vandita.kulkarni@intel.com> > Subject: Re: [PATCH] drm/i915: Fix wrong escape clock divisor init for GLK > > Op 10-07-2019 om 16:12 schreef Stanislav Lisovskiy: > > According to Bspec clock divisor registers in GeminiLake should be > > initialized by shifting 1(<<) to amount of correspondent divisor. > > While i915 was writing all this time that value as is. > > > > Surprisingly that it by accident worked, until we met some issues with > > Microtech Etab. > > > > Signed-off-by: Stanislav.Lisovskiy@intel.com > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108826 > > --- > > drivers/gpu/drm/i915/display/vlv_dsi_pll.c | 4 ++-- > > 1 file changed, 2 insertions(+), 2 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/display/vlv_dsi_pll.c > > b/drivers/gpu/drm/i915/display/vlv_dsi_pll.c > > index 99cc3e2e9c2c..f016a776a39e 100644 > > --- a/drivers/gpu/drm/i915/display/vlv_dsi_pll.c > > +++ b/drivers/gpu/drm/i915/display/vlv_dsi_pll.c > > @@ -396,8 +396,8 @@ static void glk_dsi_program_esc_clock(struct > drm_device *dev, > > else > > txesc2_div = 10; > > > > - I915_WRITE(MIPIO_TXESC_CLK_DIV1, txesc1_div & > GLK_TX_ESC_CLK_DIV1_MASK); > > - I915_WRITE(MIPIO_TXESC_CLK_DIV2, txesc2_div & > GLK_TX_ESC_CLK_DIV2_MASK); > > + I915_WRITE(MIPIO_TXESC_CLK_DIV1, (1 << (txesc1_div - 1)) & > GLK_TX_ESC_CLK_DIV1_MASK); > > + I915_WRITE(MIPIO_TXESC_CLK_DIV2, (1 << (txesc2_div - 1)) & > > +GLK_TX_ESC_CLK_DIV2_MASK); > > } The code change looks good to me. With Maarten's comment fixed, Reviewed-by: Vandita Kulkarni <vandita.kulkarni@intel.com> Regards, Vandita > > > > /* Program BXT Mipi clocks and dividers */ > > Missing a fixes tag? > > find the original commit that introduced this, then run dim fixes $commitid. > > Cheers, > > Maarten
diff --git a/drivers/gpu/drm/i915/display/vlv_dsi_pll.c b/drivers/gpu/drm/i915/display/vlv_dsi_pll.c index 99cc3e2e9c2c..f016a776a39e 100644 --- a/drivers/gpu/drm/i915/display/vlv_dsi_pll.c +++ b/drivers/gpu/drm/i915/display/vlv_dsi_pll.c @@ -396,8 +396,8 @@ static void glk_dsi_program_esc_clock(struct drm_device *dev, else txesc2_div = 10; - I915_WRITE(MIPIO_TXESC_CLK_DIV1, txesc1_div & GLK_TX_ESC_CLK_DIV1_MASK); - I915_WRITE(MIPIO_TXESC_CLK_DIV2, txesc2_div & GLK_TX_ESC_CLK_DIV2_MASK); + I915_WRITE(MIPIO_TXESC_CLK_DIV1, (1 << (txesc1_div - 1)) & GLK_TX_ESC_CLK_DIV1_MASK); + I915_WRITE(MIPIO_TXESC_CLK_DIV2, (1 << (txesc2_div - 1)) & GLK_TX_ESC_CLK_DIV2_MASK); } /* Program BXT Mipi clocks and dividers */
According to Bspec clock divisor registers in GeminiLake should be initialized by shifting 1(<<) to amount of correspondent divisor. While i915 was writing all this time that value as is. Surprisingly that it by accident worked, until we met some issues with Microtech Etab. Signed-off-by: Stanislav.Lisovskiy@intel.com Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108826 --- drivers/gpu/drm/i915/display/vlv_dsi_pll.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)