diff mbox series

[v3,6/9] drm/i915/tgl: Add VIDEO power domain

Message ID 20190730135024.31765-7-anshuman.gupta@intel.com (mailing list archive)
State New, archived
Headers show
Series DC3CO Support for TGL. | expand

Commit Message

Gupta, Anshuman July 30, 2019, 1:50 p.m. UTC 
POWER_DOMAIN_VIDEO is a hook to "DC5 Off" power well,
which can disallow DC5/6 and allow DC3CO.
It will be used when there will be PSR2 idle frame while active
video playback.

Cc: Nikula, Jani <jani.nikula@intel.com>
Cc: Deak, Imre <imre.deak@intel.com>
Cc: Manna, Animesh <animesh.manna@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_power.c | 3 +++
 drivers/gpu/drm/i915/display/intel_display_power.h | 1 +
 drivers/gpu/drm/i915/i915_drv.h                    | 6 ++++++
 3 files changed, 10 insertions(+)
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index c44b3c54cbcb..24df21e86a38 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -122,6 +122,8 @@  intel_display_power_domain_str(struct drm_i915_private *i915,
 		return "VGA";
 	case POWER_DOMAIN_AUDIO:
 		return "AUDIO";
+	case POWER_DOMAIN_VIDEO:
+		return "VIDEO";
 	case POWER_DOMAIN_AUX_A:
 		return "AUX_A";
 	case POWER_DOMAIN_AUX_B:
@@ -2774,6 +2776,7 @@  void intel_display_power_put(struct drm_i915_private *dev_priv,
 
 #define TGL_DISPLAY_DC_OFF_POWER_DOMAINS (		\
 	TGL_PW_2_POWER_DOMAINS |			\
+	BIT_ULL(POWER_DOMAIN_VIDEO) |			\
 	BIT_ULL(POWER_DOMAIN_MODESET) |			\
 	BIT_ULL(POWER_DOMAIN_AUX_A) |			\
 	BIT_ULL(POWER_DOMAIN_INIT))
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h
index 7a61cab1eb31..1dd221c4bee1 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.h
+++ b/drivers/gpu/drm/i915/display/intel_display_power.h
@@ -66,6 +66,7 @@  enum intel_display_power_domain {
 	POWER_DOMAIN_PORT_OTHER,
 	POWER_DOMAIN_VGA,
 	POWER_DOMAIN_AUDIO,
+	POWER_DOMAIN_VIDEO,
 	POWER_DOMAIN_AUX_A,
 	POWER_DOMAIN_AUX_B,
 	POWER_DOMAIN_AUX_C,
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 04e454e51a5e..8b7dbaa91a0d 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -361,6 +361,12 @@  struct intel_csr {
 	u32 allowed_dc_mask;
 	intel_wakeref_t wakeref;
 	bool prefer_dc3co;
+	intel_wakeref_t dc5_wakeref;
+	/*
+	 * Mutex to protect dc5_wakeref which make maintain proper
+	 * power domain reference count of POWER_DOMAIN_VIDEO
+	 */
+	struct mutex dc5_mutex;
 };
 
 enum i915_cache_level {