From patchwork Fri Aug 9 18:32:17 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Gupta, Anshuman" X-Patchwork-Id: 11087477 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 8D96F1398 for ; Fri, 9 Aug 2019 18:36:11 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 7D7D220223 for ; Fri, 9 Aug 2019 18:36:11 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 71E9C205F6; Fri, 9 Aug 2019 18:36:11 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 0D3D420223 for ; Fri, 9 Aug 2019 18:36:11 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 7B7946EE79; Fri, 9 Aug 2019 18:36:10 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTPS id F216A6EE79 for ; Fri, 9 Aug 2019 18:36:08 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 09 Aug 2019 11:36:08 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,366,1559545200"; d="scan'208";a="193444088" Received: from genxfsim-desktop.iind.intel.com ([10.223.74.120]) by fmsmga001.fm.intel.com with ESMTP; 09 Aug 2019 11:36:06 -0700 From: Anshuman Gupta To: intel-gfx@lists.freedesktop.org Date: Sat, 10 Aug 2019 00:02:17 +0530 Message-Id: <20190809183223.12031-4-anshuman.gupta@intel.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190809183223.12031-1-anshuman.gupta@intel.com> References: <20190809183223.12031-1-anshuman.gupta@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v5 3/9] drm/i915/tgl: Add power well to enable DC3CO state X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jani.nikula@intel.com Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP "DC3CO Off" power well inherits its power domains from "DC Off" power well, these power domains will disallow DC3CO when any external displays are connected and at time of modeset and aux programming. Renaming "DC Off" power well to "DC5 Off" power well. v2: commit log improvement. v3: Used intel_wait_for_register to wait for DC3CO exit. [Imre] Used gen9_set_dc_state() to allow/disallow DC3CO. [Imre] Moved transcoder psr2 exit line enablement from tgl_allow_dc3co() to a appropriate place haswell_crtc_enable(). [Imre] Changed the DC3CO power well enabled call back logic as recommended in review comments. [Imre] v4: Used wait_for_us() instead of intel_wait_for_reg(). [Imre (IRC)] v5: using udelay() instead of waiting for DC3CO exit status. Cc: Jani Nikula Cc: Imre Deak Cc: Animesh Manna Cc: Rodrigo Vivi Signed-off-by: Anshuman Gupta --- .../drm/i915/display/intel_display_power.c | 69 ++++++++++++++++++- 1 file changed, 67 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c index e2ef202aeeef..c9e92d48cdab 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power.c +++ b/drivers/gpu/drm/i915/display/intel_display_power.c @@ -791,7 +791,26 @@ static void gen9_set_dc_state(struct drm_i915_private *dev_priv, u32 state) dev_priv->csr.dc_state = val & mask; } -static void bxt_enable_dc9(struct drm_i915_private *dev_priv) +static void tgl_allow_dc3co(struct drm_i915_private *dev_priv) +{ + gen9_set_dc_state(dev_priv, DC_STATE_EN_DC3CO); +} + +static void tgl_disallow_dc3co(struct drm_i915_private *dev_priv) +{ + u32 val; + + val = I915_READ(DC_STATE_EN); + val &= ~DC_STATE_DC3CO_STATUS; + I915_WRITE(DC_STATE_EN, val); + gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); + /* + * Delay of 200us DC3CO Exit time B.Spec 49196 + */ + udelay(200); +} + +void bxt_enable_dc9(struct drm_i915_private *dev_priv) { assert_can_enable_dc9(dev_priv); @@ -1007,6 +1026,33 @@ static void gen9_dc_off_power_well_disable(struct drm_i915_private *dev_priv, gen9_enable_dc5(dev_priv); } +static void tgl_dc3co_power_well_enable(struct drm_i915_private *dev_priv, + struct i915_power_well *power_well) +{ + tgl_disallow_dc3co(dev_priv); +} + +static void tgl_dc3co_power_well_disable(struct drm_i915_private *dev_priv, + struct i915_power_well *power_well) +{ + if (!dev_priv->psr.sink_psr2_support) + return; + + if (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_DC3CO) + tgl_allow_dc3co(dev_priv); +} + +static bool tgl_dc3co_power_well_enabled(struct drm_i915_private *dev_priv, + struct i915_power_well *power_well) +{ + /* + * Checking alone DC_STATE_EN is not enough as DC5 power well also + * allow/disallow DC3CO to make sure both are not enabled at same time + */ + return ((I915_READ(DC_STATE_EN) & DC_STATE_EN_DC3CO) == 0 && + (I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0); +} + static void i9xx_power_well_sync_hw_noop(struct drm_i915_private *dev_priv, struct i915_power_well *power_well) { @@ -2611,6 +2657,12 @@ void intel_display_power_put(struct drm_i915_private *dev_priv, BIT_ULL(POWER_DOMAIN_TRANSCODER_VDSC_PW2) | \ BIT_ULL(POWER_DOMAIN_INIT)) +#define TGL_DISPLAY_DC3CO_OFF_POWER_DOMAINS ( \ + TGL_PW_2_POWER_DOMAINS | \ + BIT_ULL(POWER_DOMAIN_MODESET) | \ + BIT_ULL(POWER_DOMAIN_AUX_A) | \ + BIT_ULL(POWER_DOMAIN_INIT)) + #define TGL_DISPLAY_DC_OFF_POWER_DOMAINS ( \ TGL_PW_2_POWER_DOMAINS | \ BIT_ULL(POWER_DOMAIN_MODESET) | \ @@ -2715,6 +2767,13 @@ static const struct i915_power_well_ops gen9_dc_off_power_well_ops = { .is_enabled = gen9_dc_off_power_well_enabled, }; +static const struct i915_power_well_ops tgl_dc3co_power_well_ops = { + .sync_hw = i9xx_power_well_sync_hw_noop, + .enable = tgl_dc3co_power_well_enable, + .disable = tgl_dc3co_power_well_disable, + .is_enabled = tgl_dc3co_power_well_enabled, +}; + static const struct i915_power_well_ops bxt_dpio_cmn_power_well_ops = { .sync_hw = i9xx_power_well_sync_hw_noop, .enable = bxt_dpio_cmn_power_well_enable, @@ -3626,11 +3685,17 @@ static const struct i915_power_well_desc tgl_power_wells[] = { }, }, { - .name = "DC off", + .name = "DC5 off", .domains = TGL_DISPLAY_DC_OFF_POWER_DOMAINS, .ops = &gen9_dc_off_power_well_ops, .id = DISP_PW_ID_NONE, }, + { + .name = "DC3CO off", + .domains = TGL_DISPLAY_DC3CO_OFF_POWER_DOMAINS, + .ops = &tgl_dc3co_power_well_ops, + .id = DISP_PW_ID_NONE, + }, { .name = "power well 2", .domains = TGL_PW_2_POWER_DOMAINS,