From patchwork Wed Aug 21 06:32:26 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Manna, Animesh" X-Patchwork-Id: 11105561 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 46C5413A4 for ; Wed, 21 Aug 2019 06:40:20 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 2F0A0206BA for ; Wed, 21 Aug 2019 06:40:20 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 2F0A0206BA Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id C62D06E910; Wed, 21 Aug 2019 06:40:19 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTPS id BCF0F6E90D for ; Wed, 21 Aug 2019 06:40:13 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 20 Aug 2019 23:40:13 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,411,1559545200"; d="scan'208";a="195935688" Received: from amanna.iind.intel.com ([10.223.74.216]) by fmsmga001.fm.intel.com with ESMTP; 20 Aug 2019 23:40:12 -0700 From: Animesh Manna To: intel-gfx@lists.freedesktop.org Date: Wed, 21 Aug 2019 12:02:26 +0530 Message-Id: <20190821063236.19705-7-animesh.manna@intel.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20190821063236.19705-1-animesh.manna@intel.com> References: <20190821063236.19705-1-animesh.manna@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v2 06/15] drm/i915/dsb: Update i915_write to call dsb-write. X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jani Nikula Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Existing mmio-reg-write need intel_uncore handle which is part of dev_priv structure and the same design is followed by adding dsb handle in dev_priv for programming registers through DSB. I915_WRITE is modified to check for register capability and call dsb-reg-write based on its capability. No changes in I915_READ definition as DSB do not have support to read any register. Cc: Jani Nikula Cc: Rodrigo Vivi Signed-off-by: Animesh Manna --- drivers/gpu/drm/i915/display/intel_dsb.c | 2 +- drivers/gpu/drm/i915/i915_drv.h | 6 +++++- 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c index 4fe8cac6246a..6f1999140085 100644 --- a/drivers/gpu/drm/i915/display/intel_dsb.c +++ b/drivers/gpu/drm/i915/display/intel_dsb.c @@ -123,7 +123,7 @@ void intel_dsb_reg_write(struct intel_dsb *dsb, i915_reg_t reg, u32 val) u32 *buf = dsb->cmd_buf; if (!buf) { - I915_WRITE(reg, val); + intel_uncore_write(&(dev_priv)->uncore, reg, val); return; } diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 643fd6d6fd73..7aed957362c9 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1753,6 +1753,8 @@ struct drm_i915_private { /* Mutex to protect the above hdcp component related values. */ struct mutex hdcp_comp_mutex; + struct intel_dsb *dsb; + /* * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch * will be rejected. Instead look for a better place. @@ -2414,7 +2416,9 @@ int i915_reg_read_ioctl(struct drm_device *dev, void *data, intel_uncore_##op__(&(dev_priv__)->uncore, __VA_ARGS__) #define I915_READ(reg__) __I915_REG_OP(read, dev_priv, (reg__)) -#define I915_WRITE(reg__, val__) __I915_REG_OP(write, dev_priv, (reg__), (val__)) +#define I915_WRITE(reg__, val__) \ + (reg__.cap) ? intel_dsb_reg_write(dev_priv->dsb, (reg__), (val__)) : \ + __I915_REG_OP(write, dev_priv, (reg__), (val__)) #define POSTING_READ(reg__) __I915_REG_OP(posting_read, dev_priv, (reg__))