| Message ID | 20190823095232.28908-2-gwan-gyeong.mun@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/i915/dp: Support for DP HDR outputs | expand |
>-----Original Message----- >From: Mun, Gwan-gyeong >Sent: Friday, August 23, 2019 3:22 PM >To: intel-gfx@lists.freedesktop.org >Cc: dri-devel@lists.freedesktop.org; Shankar, Uma <uma.shankar@intel.com>; >Sharma, Shashank <shashank.sharma@intel.com> >Subject: [PATCH v2 1/6] drm/i915/dp: Extend program of VSC Header and DB for >Colorimetry Format > >It refactors and renames a function which handled vsc sdp header and data block >setup for supporting colorimetry format. >Function intel_dp_setup_vsc_sdp handles vsc sdp header and data block setup for >pixel encoding / colorimetry format. >In order to use colorspace information of a connector, it adds an argument of >drm_connector_state type. > >Setup VSC header and data block in function intel_dp_setup_vsc_sdp for pixel >encoding / colorimetry format as per dp 1.4a spec, section 2.2.5.7.1, table 2-119: VSC >SDP Header Bytes, section 2.2.5.7.5, table 2-120: VSC SDP Payload for DB16 through >DB18. The changes look good to me. Reviewed-by: Uma Shankar <uma.shankar@intel.com> >Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com> >--- > drivers/gpu/drm/i915/display/intel_ddi.c | 2 +- > drivers/gpu/drm/i915/display/intel_display.h | 2 - > drivers/gpu/drm/i915/display/intel_dp.c | 68 ++++++++++++++++---- > drivers/gpu/drm/i915/display/intel_dp.h | 3 + > 4 files changed, 60 insertions(+), 15 deletions(-) > >diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c >b/drivers/gpu/drm/i915/display/intel_ddi.c >index 8eb2b3ec01ed..4f7ea0a35976 100644 >--- a/drivers/gpu/drm/i915/display/intel_ddi.c >+++ b/drivers/gpu/drm/i915/display/intel_ddi.c >@@ -3475,7 +3475,7 @@ static void intel_enable_ddi_dp(struct intel_encoder >*encoder, > > intel_edp_backlight_on(crtc_state, conn_state); > intel_psr_enable(intel_dp, crtc_state); >- intel_dp_ycbcr_420_enable(intel_dp, crtc_state); >+ intel_dp_vsc_enable(intel_dp, crtc_state, conn_state); > intel_edp_drrs_enable(intel_dp, crtc_state); > > if (crtc_state->has_audio) >diff --git a/drivers/gpu/drm/i915/display/intel_display.h >b/drivers/gpu/drm/i915/display/intel_display.h >index e57e6969051d..7bd59241fc32 100644 >--- a/drivers/gpu/drm/i915/display/intel_display.h >+++ b/drivers/gpu/drm/i915/display/intel_display.h >@@ -499,8 +499,6 @@ void intel_dp_get_m_n(struct intel_crtc *crtc, > struct intel_crtc_state *pipe_config); void >intel_dp_set_m_n(const struct intel_crtc_state *crtc_state, > enum link_m_n_set m_n); >-void intel_dp_ycbcr_420_enable(struct intel_dp *intel_dp, >- const struct intel_crtc_state *crtc_state); > int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n); bool >bxt_find_best_dpll(struct intel_crtc_state *crtc_state, > struct dpll *best_clock); >diff --git a/drivers/gpu/drm/i915/display/intel_dp.c >b/drivers/gpu/drm/i915/display/intel_dp.c >index 5c45a3bb102d..55d5ab97061c 100644 >--- a/drivers/gpu/drm/i915/display/intel_dp.c >+++ b/drivers/gpu/drm/i915/display/intel_dp.c >@@ -4409,8 +4409,9 @@ u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp, >} > > static void >-intel_pixel_encoding_setup_vsc(struct intel_dp *intel_dp, >- const struct intel_crtc_state *crtc_state) >+intel_dp_setup_vsc_sdp(struct intel_dp *intel_dp, >+ const struct intel_crtc_state *crtc_state, >+ const struct drm_connector_state *conn_state) > { > struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); > struct dp_sdp vsc_sdp = {}; >@@ -4431,13 +4432,55 @@ intel_pixel_encoding_setup_vsc(struct intel_dp >*intel_dp, > */ > vsc_sdp.sdp_header.HB3 = 0x13; > >- /* >- * YCbCr 420 = 3h DB16[7:4] ITU-R BT.601 = 0h, ITU-R BT.709 = 1h >- * DB16[3:0] DP 1.4a spec, Table 2-120 >- */ >- vsc_sdp.db[16] = 0x3 << 4; /* 0x3 << 4 , YCbCr 420*/ >- /* RGB->YCBCR color conversion uses the BT.709 color space. */ >- vsc_sdp.db[16] |= 0x1; /* 0x1, ITU-R BT.709 */ >+ /* DP 1.4a spec, Table 2-120 */ >+ switch (crtc_state->output_format) { >+ case INTEL_OUTPUT_FORMAT_YCBCR444: >+ vsc_sdp.db[16] = 0x1 << 4; /* YCbCr 444 : DB16[7:4] = 1h */ >+ break; >+ case INTEL_OUTPUT_FORMAT_YCBCR420: >+ vsc_sdp.db[16] = 0x3 << 4; /* YCbCr 420 : DB16[7:4] = 3h */ >+ break; >+ case INTEL_OUTPUT_FORMAT_RGB: >+ default: >+ /* RGB: DB16[7:4] = 0h */ >+ break; >+ } >+ >+ switch (conn_state->colorspace) { >+ case DRM_MODE_COLORIMETRY_BT709_YCC: >+ vsc_sdp.db[16] |= 0x1; >+ break; >+ case DRM_MODE_COLORIMETRY_XVYCC_601: >+ vsc_sdp.db[16] |= 0x2; >+ break; >+ case DRM_MODE_COLORIMETRY_XVYCC_709: >+ vsc_sdp.db[16] |= 0x3; >+ break; >+ case DRM_MODE_COLORIMETRY_SYCC_601: >+ vsc_sdp.db[16] |= 0x4; >+ break; >+ case DRM_MODE_COLORIMETRY_OPYCC_601: >+ vsc_sdp.db[16] |= 0x5; >+ break; >+ case DRM_MODE_COLORIMETRY_BT2020_CYCC: >+ case DRM_MODE_COLORIMETRY_BT2020_RGB: >+ vsc_sdp.db[16] |= 0x6; >+ break; >+ case DRM_MODE_COLORIMETRY_BT2020_YCC: >+ vsc_sdp.db[16] |= 0x7; >+ break; >+ case DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65: >+ case DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER: >+ vsc_sdp.db[16] |= 0x4; /* DCI-P3 (SMPTE RP 431-2) */ >+ break; >+ default: >+ /* sRGB (IEC 61966-2-1) / ITU-R BT.601: DB16[0:3] = 0h */ >+ >+ /* RGB->YCBCR color conversion uses the BT.709 color space. */ >+ if (crtc_state->output_format == >INTEL_OUTPUT_FORMAT_YCBCR420) >+ vsc_sdp.db[16] |= 0x1; /* 0x1, ITU-R BT.709 */ >+ break; >+ } > > /* > * For pixel encoding formats YCbCr444, YCbCr422, YCbCr420, and Y Only, >@@ -4489,13 +4532,14 @@ intel_pixel_encoding_setup_vsc(struct intel_dp >*intel_dp, > crtc_state, DP_SDP_VSC, &vsc_sdp, sizeof(vsc_sdp)); } > >-void intel_dp_ycbcr_420_enable(struct intel_dp *intel_dp, >- const struct intel_crtc_state *crtc_state) >+void intel_dp_vsc_enable(struct intel_dp *intel_dp, >+ const struct intel_crtc_state *crtc_state, >+ const struct drm_connector_state *conn_state) > { > if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_YCBCR420) > return; > >- intel_pixel_encoding_setup_vsc(intel_dp, crtc_state); >+ intel_dp_setup_vsc_sdp(intel_dp, crtc_state, conn_state); > } > > static u8 intel_dp_autotest_link_training(struct intel_dp *intel_dp) diff --git >a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h >index 657bbb1f5ed0..91a0ee6058fe 100644 >--- a/drivers/gpu/drm/i915/display/intel_dp.h >+++ b/drivers/gpu/drm/i915/display/intel_dp.h >@@ -111,6 +111,9 @@ bool intel_dp_read_dpcd(struct intel_dp *intel_dp); bool >intel_dp_get_colorimetry_status(struct intel_dp *intel_dp); int >intel_dp_link_required(int pixel_clock, int bpp); int intel_dp_max_data_rate(int >max_link_clock, int max_lanes); >+void intel_dp_vsc_enable(struct intel_dp *intel_dp, >+ const struct intel_crtc_state *crtc_state, >+ const struct drm_connector_state *conn_state); > bool intel_digital_port_connected(struct intel_encoder *encoder); > > static inline unsigned int intel_dp_unused_lane_mask(int lane_count) >-- >2.22.0
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 8eb2b3ec01ed..4f7ea0a35976 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -3475,7 +3475,7 @@ static void intel_enable_ddi_dp(struct intel_encoder *encoder, intel_edp_backlight_on(crtc_state, conn_state); intel_psr_enable(intel_dp, crtc_state); - intel_dp_ycbcr_420_enable(intel_dp, crtc_state); + intel_dp_vsc_enable(intel_dp, crtc_state, conn_state); intel_edp_drrs_enable(intel_dp, crtc_state); if (crtc_state->has_audio) diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h index e57e6969051d..7bd59241fc32 100644 --- a/drivers/gpu/drm/i915/display/intel_display.h +++ b/drivers/gpu/drm/i915/display/intel_display.h @@ -499,8 +499,6 @@ void intel_dp_get_m_n(struct intel_crtc *crtc, struct intel_crtc_state *pipe_config); void intel_dp_set_m_n(const struct intel_crtc_state *crtc_state, enum link_m_n_set m_n); -void intel_dp_ycbcr_420_enable(struct intel_dp *intel_dp, - const struct intel_crtc_state *crtc_state); int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n); bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, struct dpll *best_clock); diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 5c45a3bb102d..55d5ab97061c 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -4409,8 +4409,9 @@ u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp, } static void -intel_pixel_encoding_setup_vsc(struct intel_dp *intel_dp, - const struct intel_crtc_state *crtc_state) +intel_dp_setup_vsc_sdp(struct intel_dp *intel_dp, + const struct intel_crtc_state *crtc_state, + const struct drm_connector_state *conn_state) { struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); struct dp_sdp vsc_sdp = {}; @@ -4431,13 +4432,55 @@ intel_pixel_encoding_setup_vsc(struct intel_dp *intel_dp, */ vsc_sdp.sdp_header.HB3 = 0x13; - /* - * YCbCr 420 = 3h DB16[7:4] ITU-R BT.601 = 0h, ITU-R BT.709 = 1h - * DB16[3:0] DP 1.4a spec, Table 2-120 - */ - vsc_sdp.db[16] = 0x3 << 4; /* 0x3 << 4 , YCbCr 420*/ - /* RGB->YCBCR color conversion uses the BT.709 color space. */ - vsc_sdp.db[16] |= 0x1; /* 0x1, ITU-R BT.709 */ + /* DP 1.4a spec, Table 2-120 */ + switch (crtc_state->output_format) { + case INTEL_OUTPUT_FORMAT_YCBCR444: + vsc_sdp.db[16] = 0x1 << 4; /* YCbCr 444 : DB16[7:4] = 1h */ + break; + case INTEL_OUTPUT_FORMAT_YCBCR420: + vsc_sdp.db[16] = 0x3 << 4; /* YCbCr 420 : DB16[7:4] = 3h */ + break; + case INTEL_OUTPUT_FORMAT_RGB: + default: + /* RGB: DB16[7:4] = 0h */ + break; + } + + switch (conn_state->colorspace) { + case DRM_MODE_COLORIMETRY_BT709_YCC: + vsc_sdp.db[16] |= 0x1; + break; + case DRM_MODE_COLORIMETRY_XVYCC_601: + vsc_sdp.db[16] |= 0x2; + break; + case DRM_MODE_COLORIMETRY_XVYCC_709: + vsc_sdp.db[16] |= 0x3; + break; + case DRM_MODE_COLORIMETRY_SYCC_601: + vsc_sdp.db[16] |= 0x4; + break; + case DRM_MODE_COLORIMETRY_OPYCC_601: + vsc_sdp.db[16] |= 0x5; + break; + case DRM_MODE_COLORIMETRY_BT2020_CYCC: + case DRM_MODE_COLORIMETRY_BT2020_RGB: + vsc_sdp.db[16] |= 0x6; + break; + case DRM_MODE_COLORIMETRY_BT2020_YCC: + vsc_sdp.db[16] |= 0x7; + break; + case DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65: + case DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER: + vsc_sdp.db[16] |= 0x4; /* DCI-P3 (SMPTE RP 431-2) */ + break; + default: + /* sRGB (IEC 61966-2-1) / ITU-R BT.601: DB16[0:3] = 0h */ + + /* RGB->YCBCR color conversion uses the BT.709 color space. */ + if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) + vsc_sdp.db[16] |= 0x1; /* 0x1, ITU-R BT.709 */ + break; + } /* * For pixel encoding formats YCbCr444, YCbCr422, YCbCr420, and Y Only, @@ -4489,13 +4532,14 @@ intel_pixel_encoding_setup_vsc(struct intel_dp *intel_dp, crtc_state, DP_SDP_VSC, &vsc_sdp, sizeof(vsc_sdp)); } -void intel_dp_ycbcr_420_enable(struct intel_dp *intel_dp, - const struct intel_crtc_state *crtc_state) +void intel_dp_vsc_enable(struct intel_dp *intel_dp, + const struct intel_crtc_state *crtc_state, + const struct drm_connector_state *conn_state) { if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_YCBCR420) return; - intel_pixel_encoding_setup_vsc(intel_dp, crtc_state); + intel_dp_setup_vsc_sdp(intel_dp, crtc_state, conn_state); } static u8 intel_dp_autotest_link_training(struct intel_dp *intel_dp) diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h index 657bbb1f5ed0..91a0ee6058fe 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.h +++ b/drivers/gpu/drm/i915/display/intel_dp.h @@ -111,6 +111,9 @@ bool intel_dp_read_dpcd(struct intel_dp *intel_dp); bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp); int intel_dp_link_required(int pixel_clock, int bpp); int intel_dp_max_data_rate(int max_link_clock, int max_lanes); +void intel_dp_vsc_enable(struct intel_dp *intel_dp, + const struct intel_crtc_state *crtc_state, + const struct drm_connector_state *conn_state); bool intel_digital_port_connected(struct intel_encoder *encoder); static inline unsigned int intel_dp_unused_lane_mask(int lane_count)
It refactors and renames a function which handled vsc sdp header and data block setup for supporting colorimetry format. Function intel_dp_setup_vsc_sdp handles vsc sdp header and data block setup for pixel encoding / colorimetry format. In order to use colorspace information of a connector, it adds an argument of drm_connector_state type. Setup VSC header and data block in function intel_dp_setup_vsc_sdp for pixel encoding / colorimetry format as per dp 1.4a spec, section 2.2.5.7.1, table 2-119: VSC SDP Header Bytes, section 2.2.5.7.5, table 2-120: VSC SDP Payload for DB16 through DB18. Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com> --- drivers/gpu/drm/i915/display/intel_ddi.c | 2 +- drivers/gpu/drm/i915/display/intel_display.h | 2 - drivers/gpu/drm/i915/display/intel_dp.c | 68 ++++++++++++++++---- drivers/gpu/drm/i915/display/intel_dp.h | 3 + 4 files changed, 60 insertions(+), 15 deletions(-)