From patchwork Wed Sep 18 09:22:01 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stanislav Lisovskiy X-Patchwork-Id: 11149933 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 10BF01599 for ; Wed, 18 Sep 2019 09:24:21 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id EAE4F214AF for ; Wed, 18 Sep 2019 09:24:20 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org EAE4F214AF Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 497276EE77; Wed, 18 Sep 2019 09:24:20 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id 4E48F6EE77 for ; Wed, 18 Sep 2019 09:24:19 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga105.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 18 Sep 2019 02:24:18 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,520,1559545200"; d="scan'208";a="270813458" Received: from slisovsk-lenovo-ideapad-720s-13ikb.fi.intel.com ([10.237.72.89]) by orsmga001.jf.intel.com with ESMTP; 18 Sep 2019 02:24:16 -0700 From: Stanislav Lisovskiy To: intel-gfx@lists.freedesktop.org Date: Wed, 18 Sep 2019 12:22:01 +0300 Message-Id: <20190918092201.679-1-stanislav.lisovskiy@intel.com> X-Mailer: git-send-email 2.17.1 Subject: [Intel-gfx] [PATCH v2] drm/i915: Add TigerLake bandwidth checking X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ville.syrjala@intel.com, martin.peres@intel.com MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Added bandwidth calculation algorithm and checks, similar way as it was done for ICL, some constants were corrected according to BSpec. Signed-off-by: Stanislav Lisovskiy v2: Start using same icl_get_bw_info function to avoid code duplication. Moved mpagesize to memory info related structure as it is now dependant on memory type. Fixed qi.t_bl field assignment. Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=111600 --- drivers/gpu/drm/i915/display/intel_bw.c | 31 ++++++++++++++++++++----- 1 file changed, 25 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c index 688858ebe4d0..c89fcdccac7e 100644 --- a/drivers/gpu/drm/i915/display/intel_bw.c +++ b/drivers/gpu/drm/i915/display/intel_bw.c @@ -19,6 +19,7 @@ struct intel_qgv_info { u8 num_points; u8 num_channels; u8 t_bl; + u8 mpagesize; enum intel_dram_type dram_type; }; @@ -56,7 +57,13 @@ static int icl_pcode_read_mem_global_info(struct drm_i915_private *dev_priv, qi->num_channels = (val & 0xf0) >> 4; qi->num_points = (val & 0xf00) >> 8; - qi->t_bl = qi->dram_type == INTEL_DRAM_DDR4 ? 4 : 8; + if (IS_GEN(dev_priv, 11)) { + qi->mpagesize = 16; + qi->t_bl = qi->dram_type == INTEL_DRAM_DDR4 ? 4 : 8; + } else if (IS_GEN(dev_priv, 12)) { + qi->mpagesize = qi->dram_type == INTEL_DRAM_DDR4 ? 16 : 32; + qi->t_bl = qi->dram_type == INTEL_DRAM_DDR4 ? 4 : 16; + } return 0; } @@ -132,20 +139,26 @@ static int icl_sagv_max_dclk(const struct intel_qgv_info *qi) } struct intel_sa_info { - u8 deburst, mpagesize, deprogbwlimit, displayrtids; + u16 displayrtids; + u8 deburst, deprogbwlimit; }; static const struct intel_sa_info icl_sa_info = { .deburst = 8, - .mpagesize = 16, .deprogbwlimit = 25, /* GB/s */ .displayrtids = 128, }; -static int icl_get_bw_info(struct drm_i915_private *dev_priv) +static const struct intel_sa_info tgl_sa_info = { + .deburst = 16, + .deprogbwlimit = 34, /* GB/s */ + .displayrtids = 256, +}; + + +static int icl_get_bw_info(struct drm_i915_private *dev_priv, const struct intel_sa_info *sa) { struct intel_qgv_info qi = {}; - const struct intel_sa_info *sa = &icl_sa_info; bool is_y_tile = true; /* assume y tile may be used */ int num_channels; int deinterleave; @@ -234,7 +247,9 @@ static unsigned int icl_max_bw(struct drm_i915_private *dev_priv, void intel_bw_init_hw(struct drm_i915_private *dev_priv) { if (IS_GEN(dev_priv, 11)) - icl_get_bw_info(dev_priv); + icl_get_bw_info(dev_priv, &icl_sa_info); + else if (IS_GEN(dev_priv, 12)) + icl_get_bw_info(dev_priv, &tgl_sa_info); } static unsigned int intel_max_data_rate(struct drm_i915_private *dev_priv, @@ -249,6 +264,10 @@ static unsigned int intel_max_data_rate(struct drm_i915_private *dev_priv, return min3(icl_max_bw(dev_priv, num_planes, 0), icl_max_bw(dev_priv, num_planes, 1), icl_max_bw(dev_priv, num_planes, 2)); + else if (IS_GEN(dev_priv, 12)) + return min3(icl_max_bw(dev_priv, num_planes, 0), + icl_max_bw(dev_priv, num_planes, 1), + icl_max_bw(dev_priv, num_planes, 2)); else return UINT_MAX; }