From patchwork Thu Oct 3 15:06:48 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Manna, Animesh" X-Patchwork-Id: 11172767 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 2C68613B1 for ; Thu, 3 Oct 2019 15:15:32 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 145D220700 for ; Thu, 3 Oct 2019 15:15:32 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 145D220700 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 801716EA0B; Thu, 3 Oct 2019 15:15:31 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by gabe.freedesktop.org (Postfix) with ESMTPS id 04EAE6EA0B for ; Thu, 3 Oct 2019 15:15:29 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga105.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 03 Oct 2019 08:15:29 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.67,252,1566889200"; d="scan'208";a="391976232" Received: from amanna.iind.intel.com ([10.223.74.216]) by fmsmga005.fm.intel.com with ESMTP; 03 Oct 2019 08:15:26 -0700 From: Animesh Manna To: intel-gfx@lists.freedesktop.org Date: Thu, 3 Oct 2019 20:36:48 +0530 Message-Id: <20191003150653.15881-2-animesh.manna@intel.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20191003150653.15881-1-animesh.manna@intel.com> References: <20191003150653.15881-1-animesh.manna@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [RFC 1/6] drm/dp: get/set phy compliance pattern. X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jani.nikula@intel.com Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" During phy complaince auto test mode source need to read requested test pattern from sink through DPCD. After processing the request source need to set the pattern. So set/get method added in drm layer as it is DP protocol. Signed-off-by: Animesh Manna --- drivers/gpu/drm/drm_dp_helper.c | 77 +++++++++++++++++++++++++++++++++ include/drm/drm_dp_helper.h | 28 ++++++++++++ 2 files changed, 105 insertions(+) diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c index f373798d82f6..3cb7170e55f4 100644 --- a/drivers/gpu/drm/drm_dp_helper.c +++ b/drivers/gpu/drm/drm_dp_helper.c @@ -1484,3 +1484,80 @@ int drm_dp_dsc_sink_supported_input_bpcs(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_S return num_bpc; } EXPORT_SYMBOL(drm_dp_dsc_sink_supported_input_bpcs); + +/** + * drm_dp_get_phy_test_pattern() - get the requested pattern from the sink. + * @aux: DisplayPort AUX channel + * @data: DP phy compliance test parameters. + * + * Returns 0 on success or a negative error code on failure. + */ +int drm_dp_get_phy_test_pattern(struct drm_dp_aux *aux, + struct drm_dp_phy_test_params *data) +{ + int err; + + err = drm_dp_link_probe(aux, &data->link); + if (err < 0) + return err; + + err = drm_dp_dpcd_read(aux, DP_TEST_PHY_PATTERN, &data->phy_pattern, 1); + if (err < 0) + return err; + + switch (data->phy_pattern) { + case DP_TEST_PHY_PATTERN_80BIT_CUSTOM: + err = drm_dp_dpcd_read(aux, DP_TEST_80BIT_CUSTOM_PATTERN_7_0, + &data->custom80, 10); + if (err < 0) + return err; + + break; + case DP_TEST_PHY_PATTERN_CP2520: + err = drm_dp_dpcd_read(aux, DP_TEST_HBR2_SCRAMBLER_RESET, + &data->hbr2_reset, 2); + if (err < 0) + return err; + } + + return 0; +} +EXPORT_SYMBOL(drm_dp_get_phy_test_pattern); + +/** + * drm_dp_set_phy_test_pattern() - set the pattern to the sink. + * @aux: DisplayPort AUX channel + * @data: DP phy compliance test parameters. + * + * Returns 0 on success or a negative error code on failure. + */ +int drm_dp_set_phy_test_pattern(struct drm_dp_aux *aux, + struct drm_dp_phy_test_params *data) +{ + int err, i; + u8 test_pattern; + + err = drm_dp_link_configure(aux, &data->link); + if (err < 0) + return err; + + test_pattern = data->phy_pattern; + if (data->link.revision < 0x12) { + test_pattern = (test_pattern << 2) & + DP_LINK_QUAL_PATTERN_11_MASK; + err = drm_dp_dpcd_write(aux, DP_TRAINING_PATTERN_SET, + &test_pattern, 1); + if (err < 0) + return err; + } else { + for (i = 0; i < data->link.num_lanes; i++) { + err = drm_dp_dpcd_write(aux, DP_LINK_QUAL_LANE0_SET + i, + &test_pattern, 1); + if (err < 0) + return err; + } + } + + return 0; +} +EXPORT_SYMBOL(drm_dp_set_phy_test_pattern); diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h index ed1a985745ba..77dcf5879beb 100644 --- a/include/drm/drm_dp_helper.h +++ b/include/drm/drm_dp_helper.h @@ -691,6 +691,14 @@ # define DP_TEST_COUNT_MASK 0xf #define DP_TEST_PHY_PATTERN 0x248 +# define DP_TEST_PHY_PATTERN_NONE 0 +# define DP_TEST_PHY_PATTERN_D10_2 1 +# define DP_TEST_PHY_PATTERN_ERROR_COUNT 2 +# define DP_TEST_PHY_PATTERN_PRBS7 3 +# define DP_TEST_PHY_PATTERN_80BIT_CUSTOM 4 +# define DP_TEST_PHY_PATTERN_CP2520 5 + +#define DP_TEST_HBR2_SCRAMBLER_RESET 0x24A #define DP_TEST_80BIT_CUSTOM_PATTERN_7_0 0x250 #define DP_TEST_80BIT_CUSTOM_PATTERN_15_8 0x251 #define DP_TEST_80BIT_CUSTOM_PATTERN_23_16 0x252 @@ -1523,4 +1531,24 @@ static inline void drm_dp_cec_unset_edid(struct drm_dp_aux *aux) #endif +/** + * struct drm_dp_phy_test_params - DP Phy Compliance parameters + * @link: Link information. + * @phy_pattern: DP Phy test pattern from DPCD 0x248 (sink) + * @hb2_reset: DP HBR2_COMPLIANCE_SCRAMBLER_RESET from DCPD + * 0x24A and 0x24B (sink) + * @custom80: DP Test_80BIT_CUSTOM_PATTERN from DPCDs 0x250 + * through 0x259. + */ +struct drm_dp_phy_test_params { + struct drm_dp_link link; + u8 phy_pattern; + u8 hbr2_reset[2]; + u8 custom80[10]; +}; + +int drm_dp_get_phy_test_pattern(struct drm_dp_aux *aux, + struct drm_dp_phy_test_params *data); +int drm_dp_set_phy_test_pattern(struct drm_dp_aux *aux, + struct drm_dp_phy_test_params *data); #endif /* _DRM_DP_HELPER_H_ */