| Message ID | 20191014110122.31923-7-vandita.kulkarni@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add mipi dsi command mode support. | expand |
Correction in this patch is needed , I will make the below change in the next version. > -----Original Message----- > From: Kulkarni, Vandita <vandita.kulkarni@intel.com> > Sent: Monday, October 14, 2019 4:31 PM > To: intel-gfx@lists.freedesktop.org > Cc: Nikula, Jani <jani.nikula@intel.com>; ville.syrjala@linux.intel.com; > Shankar, Uma <uma.shankar@intel.com>; Kulkarni, Vandita > <vandita.kulkarni@intel.com> > Subject: [RFC 6/7] drm/i915/dsi: Add TE handler for dsi cmd mode. > > In case of dual link, we get the TE on slave. > So clear the TE on slave DSI IIR. > > Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com> > --- > drivers/gpu/drm/i915/i915_irq.c | 61 > +++++++++++++++++++++++++++++++++ > 1 file changed, 61 insertions(+) > > diff --git a/drivers/gpu/drm/i915/i915_irq.c > b/drivers/gpu/drm/i915/i915_irq.c index bfb2a63504fb..d12efa72943b > 100644 > --- a/drivers/gpu/drm/i915/i915_irq.c > +++ b/drivers/gpu/drm/i915/i915_irq.c > @@ -2628,6 +2628,61 @@ gen8_de_misc_irq_handler(struct > drm_i915_private *dev_priv, u32 iir) > DRM_ERROR("Unexpected DE Misc interrupt\n"); } > > +void gen11_dsi_te_interrupt_handler(struct drm_i915_private *dev_priv, > + u32 iir_value) > +{ > + enum pipe pipe = INVALID_PIPE; > + enum port port; > + enum transcoder dsi_trans; > + u32 val; > + > + /* > + * Incase of dual link, TE comes from DSI_1 > + * this is to check if dual link is enabled > + */ > + val = I915_READ(TRANS_DDI_FUNC_CTL2(TRANSCODER_DSI_0)); > + val &= PORT_SYNC_MODE_ENABLE; > + > + /* > + * if dual link is enabled, then read DSI_0 > + * transcoder registers > + */ > + port = ((iir_value & ICL_DSI_1) && val) || (iir_value & ICL_DSI_0) ? > PORT_A : PORT_B; > + dsi_trans = (port == PORT_A) ? TRANSCODER_DSI_0 : > TRANSCODER_DSI_1; > + > + /* Check if DSI configured in command mode */ > + val = I915_READ(DSI_TRANS_FUNC_CONF(dsi_trans)); > + val = (val & OP_MODE_MASK) >> 28; > + > + if (val) { > + DRM_ERROR("DSI trancoder not configured in command > mode\n"); > + return; > + } > + > + /* Get PIPE for handling VBLANK event */ > + val = I915_READ(TRANS_DDI_FUNC_CTL(dsi_trans)); > + switch (val & TRANS_DDI_EDP_INPUT_MASK) { > + case TRANS_DDI_EDP_INPUT_A_ON: > + pipe = PIPE_A; > + break; > + case TRANS_DDI_EDP_INPUT_B_ONOFF: > + pipe = PIPE_B; > + break; > + case TRANS_DDI_EDP_INPUT_C_ONOFF: > + pipe = PIPE_C; > + break; > + default: > + DRM_ERROR("Invalid PIPE\n"); > + } > + > + /* clear TE in dsi IIR */ > + port = (iir_value & ICL_DSI_1) ? PORT_B : PORT_A; > + val = I915_READ(ICL_DSI_INTR_IDENT_REG(port)); > + I915_WRITE((ICL_DSI_INTR_IDENT_REG(port)), val); > + > + drm_handle_vblank(&dev_priv->drm, pipe); } > + > static irqreturn_t > gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl) { > @@ -2692,6 +2747,12 @@ gen8_de_irq_handler(struct drm_i915_private > *dev_priv, u32 master_ctl) > found = true; > } > > + if ((INTEL_GEN(dev_priv) >= 11) && > + (iir & (ICL_DSI_0 | ICL_DSI_1))) { Instead if ICL_DSI_0 it should be ICL_TE_DSI_0 and instead of ICL_DSI_1 it should be ICL_TE_DSI_1 > + gen11_dsi_te_interrupt_handler(dev_priv, > iir); > + found = true; > + } > + > if (!found) > DRM_ERROR("Unexpected DE Port > interrupt\n"); > } > -- > 2.21.0.5.gaeb582a
On 2019-10-14 at 16:31:21 +0530, Vandita Kulkarni wrote: > In case of dual link, we get the TE on slave. > So clear the TE on slave DSI IIR. > > Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com> > --- > drivers/gpu/drm/i915/i915_irq.c | 61 +++++++++++++++++++++++++++++++++ > 1 file changed, 61 insertions(+) > > diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c > index bfb2a63504fb..d12efa72943b 100644 > --- a/drivers/gpu/drm/i915/i915_irq.c > +++ b/drivers/gpu/drm/i915/i915_irq.c > @@ -2628,6 +2628,61 @@ gen8_de_misc_irq_handler(struct drm_i915_private *dev_priv, u32 iir) > DRM_ERROR("Unexpected DE Misc interrupt\n"); > } > > +void gen11_dsi_te_interrupt_handler(struct drm_i915_private *dev_priv, > + u32 iir_value) > +{ > + enum pipe pipe = INVALID_PIPE; > + enum port port; > + enum transcoder dsi_trans; > + u32 val; usually we order the declarations based on the length. > + > + /* > + * Incase of dual link, TE comes from DSI_1 > + * this is to check if dual link is enabled > + */ > + val = I915_READ(TRANS_DDI_FUNC_CTL2(TRANSCODER_DSI_0)); > + val &= PORT_SYNC_MODE_ENABLE; > + > + /* > + * if dual link is enabled, then read DSI_0 > + * transcoder registers > + */ > + port = ((iir_value & ICL_DSI_1) && val) || (iir_value & ICL_DSI_0) ? PORT_A : PORT_B; wrap it!? beyond 80char? > + dsi_trans = (port == PORT_A) ? TRANSCODER_DSI_0 : TRANSCODER_DSI_1; > + > + /* Check if DSI configured in command mode */ > + val = I915_READ(DSI_TRANS_FUNC_CONF(dsi_trans)); > + val = (val & OP_MODE_MASK) >> 28; Could we use a macro, like GET_OP_MODE()? > + > + if (val) { > + DRM_ERROR("DSI trancoder not configured in command mode\n"); > + return; > + } > + > + /* Get PIPE for handling VBLANK event */ > + val = I915_READ(TRANS_DDI_FUNC_CTL(dsi_trans)); > + switch (val & TRANS_DDI_EDP_INPUT_MASK) { > + case TRANS_DDI_EDP_INPUT_A_ON: > + pipe = PIPE_A; > + break; > + case TRANS_DDI_EDP_INPUT_B_ONOFF: > + pipe = PIPE_B; > + break; > + case TRANS_DDI_EDP_INPUT_C_ONOFF: > + pipe = PIPE_C; > + break; > + default: > + DRM_ERROR("Invalid PIPE\n"); > + } > + > + /* clear TE in dsi IIR */ > + port = (iir_value & ICL_DSI_1) ? PORT_B : PORT_A; > + val = I915_READ(ICL_DSI_INTR_IDENT_REG(port)); > + I915_WRITE((ICL_DSI_INTR_IDENT_REG(port)), val); extra () around ICL_DSI_INTR_IDENT_REG(port) > + > + drm_handle_vblank(&dev_priv->drm, pipe); > +} > + > static irqreturn_t > gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl) > { > @@ -2692,6 +2747,12 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl) > found = true; > } > > + if ((INTEL_GEN(dev_priv) >= 11) && > + (iir & (ICL_DSI_0 | ICL_DSI_1))) { alignment. -Ram > + gen11_dsi_te_interrupt_handler(dev_priv, iir); > + found = true; > + } > + > if (!found) > DRM_ERROR("Unexpected DE Port interrupt\n"); > } > -- > 2.21.0.5.gaeb582a > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> -----Original Message----- > From: C, Ramalingam <ramalingam.c@intel.com> > Sent: Wednesday, October 16, 2019 3:55 PM > To: Kulkarni, Vandita <vandita.kulkarni@intel.com> > Cc: intel-gfx@lists.freedesktop.org; Nikula, Jani <jani.nikula@intel.com> > Subject: Re: [Intel-gfx] [RFC 6/7] drm/i915/dsi: Add TE handler for dsi cmd > mode. > > On 2019-10-14 at 16:31:21 +0530, Vandita Kulkarni wrote: > > In case of dual link, we get the TE on slave. > > So clear the TE on slave DSI IIR. > > > > Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com> > > --- > > drivers/gpu/drm/i915/i915_irq.c | 61 > > +++++++++++++++++++++++++++++++++ > > 1 file changed, 61 insertions(+) > > > > diff --git a/drivers/gpu/drm/i915/i915_irq.c > > b/drivers/gpu/drm/i915/i915_irq.c index bfb2a63504fb..d12efa72943b > > 100644 > > --- a/drivers/gpu/drm/i915/i915_irq.c > > +++ b/drivers/gpu/drm/i915/i915_irq.c > > @@ -2628,6 +2628,61 @@ gen8_de_misc_irq_handler(struct > drm_i915_private *dev_priv, u32 iir) > > DRM_ERROR("Unexpected DE Misc interrupt\n"); } > > > > +void gen11_dsi_te_interrupt_handler(struct drm_i915_private *dev_priv, > > + u32 iir_value) > > +{ > > + enum pipe pipe = INVALID_PIPE; > > + enum port port; > > + enum transcoder dsi_trans; > > + u32 val; > usually we order the declarations based on the length. Okay. > > + > > + /* > > + * Incase of dual link, TE comes from DSI_1 > > + * this is to check if dual link is enabled > > + */ > > + val = I915_READ(TRANS_DDI_FUNC_CTL2(TRANSCODER_DSI_0)); > > + val &= PORT_SYNC_MODE_ENABLE; > > + > > + /* > > + * if dual link is enabled, then read DSI_0 > > + * transcoder registers > > + */ > > + port = ((iir_value & ICL_DSI_1) && val) || (iir_value & ICL_DSI_0) ? > > +PORT_A : PORT_B; > wrap it!? beyond 80char? Okay. > > + dsi_trans = (port == PORT_A) ? TRANSCODER_DSI_0 : > TRANSCODER_DSI_1; > > + > > + /* Check if DSI configured in command mode */ > > + val = I915_READ(DSI_TRANS_FUNC_CONF(dsi_trans)); > > + val = (val & OP_MODE_MASK) >> 28; > Could we use a macro, like GET_OP_MODE()? Ok, will check. > > + > > + if (val) { > > + DRM_ERROR("DSI trancoder not configured in command > mode\n"); > > + return; > > + } > > + > > + /* Get PIPE for handling VBLANK event */ > > + val = I915_READ(TRANS_DDI_FUNC_CTL(dsi_trans)); > > + switch (val & TRANS_DDI_EDP_INPUT_MASK) { > > + case TRANS_DDI_EDP_INPUT_A_ON: > > + pipe = PIPE_A; > > + break; > > + case TRANS_DDI_EDP_INPUT_B_ONOFF: > > + pipe = PIPE_B; > > + break; > > + case TRANS_DDI_EDP_INPUT_C_ONOFF: > > + pipe = PIPE_C; > > + break; > > + default: > > + DRM_ERROR("Invalid PIPE\n"); > > + } > > + > > + /* clear TE in dsi IIR */ > > + port = (iir_value & ICL_DSI_1) ? PORT_B : PORT_A; > > + val = I915_READ(ICL_DSI_INTR_IDENT_REG(port)); > > + I915_WRITE((ICL_DSI_INTR_IDENT_REG(port)), val); > extra () around ICL_DSI_INTR_IDENT_REG(port) Okay. > > + > > + drm_handle_vblank(&dev_priv->drm, pipe); } > > + > > static irqreturn_t > > gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 > > master_ctl) { @@ -2692,6 +2747,12 @@ gen8_de_irq_handler(struct > > drm_i915_private *dev_priv, u32 master_ctl) > > found = true; > > } > > > > + if ((INTEL_GEN(dev_priv) >= 11) && > > + (iir & (ICL_DSI_0 | ICL_DSI_1))) { > alignment. Will fix this, also it needs to be fixed with ICL_DSI_0_TE and ICL_DSI_1_TE. Thanks Vandita > > -Ram > > + gen11_dsi_te_interrupt_handler(dev_priv, > iir); > > + found = true; > > + } > > + > > if (!found) > > DRM_ERROR("Unexpected DE Port > interrupt\n"); > > } > > -- > > 2.21.0.5.gaeb582a > > > > _______________________________________________ > > Intel-gfx mailing list > > Intel-gfx@lists.freedesktop.org > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index bfb2a63504fb..d12efa72943b 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -2628,6 +2628,61 @@ gen8_de_misc_irq_handler(struct drm_i915_private *dev_priv, u32 iir) DRM_ERROR("Unexpected DE Misc interrupt\n"); } +void gen11_dsi_te_interrupt_handler(struct drm_i915_private *dev_priv, + u32 iir_value) +{ + enum pipe pipe = INVALID_PIPE; + enum port port; + enum transcoder dsi_trans; + u32 val; + + /* + * Incase of dual link, TE comes from DSI_1 + * this is to check if dual link is enabled + */ + val = I915_READ(TRANS_DDI_FUNC_CTL2(TRANSCODER_DSI_0)); + val &= PORT_SYNC_MODE_ENABLE; + + /* + * if dual link is enabled, then read DSI_0 + * transcoder registers + */ + port = ((iir_value & ICL_DSI_1) && val) || (iir_value & ICL_DSI_0) ? PORT_A : PORT_B; + dsi_trans = (port == PORT_A) ? TRANSCODER_DSI_0 : TRANSCODER_DSI_1; + + /* Check if DSI configured in command mode */ + val = I915_READ(DSI_TRANS_FUNC_CONF(dsi_trans)); + val = (val & OP_MODE_MASK) >> 28; + + if (val) { + DRM_ERROR("DSI trancoder not configured in command mode\n"); + return; + } + + /* Get PIPE for handling VBLANK event */ + val = I915_READ(TRANS_DDI_FUNC_CTL(dsi_trans)); + switch (val & TRANS_DDI_EDP_INPUT_MASK) { + case TRANS_DDI_EDP_INPUT_A_ON: + pipe = PIPE_A; + break; + case TRANS_DDI_EDP_INPUT_B_ONOFF: + pipe = PIPE_B; + break; + case TRANS_DDI_EDP_INPUT_C_ONOFF: + pipe = PIPE_C; + break; + default: + DRM_ERROR("Invalid PIPE\n"); + } + + /* clear TE in dsi IIR */ + port = (iir_value & ICL_DSI_1) ? PORT_B : PORT_A; + val = I915_READ(ICL_DSI_INTR_IDENT_REG(port)); + I915_WRITE((ICL_DSI_INTR_IDENT_REG(port)), val); + + drm_handle_vblank(&dev_priv->drm, pipe); +} + static irqreturn_t gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl) { @@ -2692,6 +2747,12 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl) found = true; } + if ((INTEL_GEN(dev_priv) >= 11) && + (iir & (ICL_DSI_0 | ICL_DSI_1))) { + gen11_dsi_te_interrupt_handler(dev_priv, iir); + found = true; + } + if (!found) DRM_ERROR("Unexpected DE Port interrupt\n"); }
In case of dual link, we get the TE on slave. So clear the TE on slave DSI IIR. Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com> --- drivers/gpu/drm/i915/i915_irq.c | 61 +++++++++++++++++++++++++++++++++ 1 file changed, 61 insertions(+)