| Message ID | 20191023120618.5344-1-tapani.palli@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/i915/tgl: whitelist PS_(DEPTH|INVOCATION)_COUNT | expand |
Quoting Tapani Pälli (2019-10-23 13:06:18) > As with commit 3fe0107e45ab, this change fixes multiple tests that are > using the invocation counts. Documentation doesn't list the workaround > for TGL but applying it fixes the tests. > > Signed-off-by: Tapani Pälli <tapani.palli@intel.com> Acked-by: Chris Wilson <chris@chris-wilson.co.uk> -Chris
On 23/10/2019 15:06, Tapani Pälli wrote: > As with commit 3fe0107e45ab, this change fixes multiple tests that are > using the invocation counts. Documentation doesn't list the workaround > for TGL but applying it fixes the tests. > > Signed-off-by: Tapani Pälli <tapani.palli@intel.com> Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> > --- > drivers/gpu/drm/i915/gt/intel_workarounds.c | 20 ++++++++++++++++++++ > 1 file changed, 20 insertions(+) > > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c > index af8a8183154a..86ded203b2dd 100644 > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c > @@ -1215,6 +1215,26 @@ static void icl_whitelist_build(struct intel_engine_cs *engine) > > static void tgl_whitelist_build(struct intel_engine_cs *engine) > { > + struct i915_wa_list *w = &engine->whitelist; > + > + switch (engine->class) { > + case RENDER_CLASS: > + /* > + * WaAllowPMDepthAndInvocationCountAccessFromUMD:tgl > + * > + * This covers 4 registers which are next to one another : > + * - PS_INVOCATION_COUNT > + * - PS_INVOCATION_COUNT_UDW > + * - PS_DEPTH_COUNT > + * - PS_DEPTH_COUNT_UDW > + */ > + whitelist_reg_ext(w, PS_INVOCATION_COUNT, > + RING_FORCE_TO_NONPRIV_ACCESS_RD | > + RING_FORCE_TO_NONPRIV_RANGE_4); > + break; > + default: > + break; > + } > } > > void intel_engine_init_whitelist(struct intel_engine_cs *engine)
Tapani Pälli <tapani.palli@intel.com> writes: > As with commit 3fe0107e45ab, this change fixes multiple tests that are > using the invocation counts. Documentation doesn't list the workaround > for TGL but applying it fixes the tests. > > Signed-off-by: Tapani Pälli <tapani.palli@intel.com> > --- > drivers/gpu/drm/i915/gt/intel_workarounds.c | 20 ++++++++++++++++++++ > 1 file changed, 20 insertions(+) > > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c > index af8a8183154a..86ded203b2dd 100644 > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c > @@ -1215,6 +1215,26 @@ static void icl_whitelist_build(struct intel_engine_cs *engine) > > static void tgl_whitelist_build(struct intel_engine_cs *engine) > { > + struct i915_wa_list *w = &engine->whitelist; > + > + switch (engine->class) { > + case RENDER_CLASS: > + /* > + * WaAllowPMDepthAndInvocationCountAccessFromUMD:tgl Tried to find info about this but failed. > + * > + * This covers 4 registers which are next to one another : > + * - PS_INVOCATION_COUNT > + * - PS_INVOCATION_COUNT_UDW > + * - PS_DEPTH_COUNT > + * - PS_DEPTH_COUNT_UDW > + */ > + whitelist_reg_ext(w, PS_INVOCATION_COUNT, > + RING_FORCE_TO_NONPRIV_ACCESS_RD | > + RING_FORCE_TO_NONPRIV_RANGE_4); The register spec is identical with gen11 so ok to whitelist. Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> > + break; > + default: > + break; > + } > } > > void intel_engine_init_whitelist(struct intel_engine_cs *engine) > -- > 2.21.0 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
On 23/10/2019 19:12, Mika Kuoppala wrote: > Tapani Pälli <tapani.palli@intel.com> writes: > >> As with commit 3fe0107e45ab, this change fixes multiple tests that are >> using the invocation counts. Documentation doesn't list the workaround >> for TGL but applying it fixes the tests. >> >> Signed-off-by: Tapani Pälli <tapani.palli@intel.com> >> --- >> drivers/gpu/drm/i915/gt/intel_workarounds.c | 20 ++++++++++++++++++++ >> 1 file changed, 20 insertions(+) >> >> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c >> index af8a8183154a..86ded203b2dd 100644 >> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c >> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c >> @@ -1215,6 +1215,26 @@ static void icl_whitelist_build(struct intel_engine_cs *engine) >> >> static void tgl_whitelist_build(struct intel_engine_cs *engine) >> { >> + struct i915_wa_list *w = &engine->whitelist; >> + >> + switch (engine->class) { >> + case RENDER_CLASS: >> + /* >> + * WaAllowPMDepthAndInvocationCountAccessFromUMD:tgl > Tried to find info about this but failed. It probably got renamed, it started with CFL stepping C+ and wasn't listed for ICL. ¯\_(ツ)_/¯ -Lionel > >> + * >> + * This covers 4 registers which are next to one another : >> + * - PS_INVOCATION_COUNT >> + * - PS_INVOCATION_COUNT_UDW >> + * - PS_DEPTH_COUNT >> + * - PS_DEPTH_COUNT_UDW >> + */ >> + whitelist_reg_ext(w, PS_INVOCATION_COUNT, >> + RING_FORCE_TO_NONPRIV_ACCESS_RD | >> + RING_FORCE_TO_NONPRIV_RANGE_4); > The register spec is identical with gen11 so ok to whitelist. > > Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> > >> + break; >> + default: >> + break; >> + } >> } >> >> void intel_engine_init_whitelist(struct intel_engine_cs *engine) >> -- >> 2.21.0 >> >> _______________________________________________ >> Intel-gfx mailing list >> Intel-gfx@lists.freedesktop.org >> https://lists.freedesktop.org/mailman/listinfo/intel-gfx > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Quoting Patchwork (2019-10-23 22:20:49) > * igt@i915_selftest@live_workarounds: > - {fi-tgl-u}: [PASS][3] -> [DMESG-FAIL][4] > [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7165/fi-tgl-u/igt@i915_selftest@live_workarounds.html > [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14947/fi-tgl-u/igt@i915_selftest@live_workarounds.html That does seem to be genuine and worth following up with. -Chris
On 10/24/19 12:49 AM, Chris Wilson wrote: > Quoting Patchwork (2019-10-23 22:20:49) >> * igt@i915_selftest@live_workarounds: >> - {fi-tgl-u}: [PASS][3] -> [DMESG-FAIL][4] >> [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7165/fi-tgl-u/igt@i915_selftest@live_workarounds.html >> [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14947/fi-tgl-u/igt@i915_selftest@live_workarounds.html > > That does seem to be genuine and worth following up with. > -Chris > Yes, I've reproduced this locally. Any ideas appreciated here .. Thanks; // Tapani
Quoting Tapani Pälli (2019-10-24 07:39:50) > > > On 10/24/19 12:49 AM, Chris Wilson wrote: > > Quoting Patchwork (2019-10-23 22:20:49) > >> * igt@i915_selftest@live_workarounds: > >> - {fi-tgl-u}: [PASS][3] -> [DMESG-FAIL][4] > >> [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7165/fi-tgl-u/igt@i915_selftest@live_workarounds.html > >> [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14947/fi-tgl-u/igt@i915_selftest@live_workarounds.html > > > > That does seem to be genuine and worth following up with. > > -Chris > > > > Yes, I've reproduced this locally. Any ideas appreciated here .. There are two things the test can take care of, stripping the high bit and replicating the fuzzing across the entire range. Stripping the high bit is /likely/ enough to circumvent the issue (depending on root cause of the issue). But the GPU is not meant to hang on bogus LRI; the HW validator is meant to no-op them. -Chris
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index af8a8183154a..86ded203b2dd 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -1215,6 +1215,26 @@ static void icl_whitelist_build(struct intel_engine_cs *engine) static void tgl_whitelist_build(struct intel_engine_cs *engine) { + struct i915_wa_list *w = &engine->whitelist; + + switch (engine->class) { + case RENDER_CLASS: + /* + * WaAllowPMDepthAndInvocationCountAccessFromUMD:tgl + * + * This covers 4 registers which are next to one another : + * - PS_INVOCATION_COUNT + * - PS_INVOCATION_COUNT_UDW + * - PS_DEPTH_COUNT + * - PS_DEPTH_COUNT_UDW + */ + whitelist_reg_ext(w, PS_INVOCATION_COUNT, + RING_FORCE_TO_NONPRIV_ACCESS_RD | + RING_FORCE_TO_NONPRIV_RANGE_4); + break; + default: + break; + } } void intel_engine_init_whitelist(struct intel_engine_cs *engine)
As with commit 3fe0107e45ab, this change fixes multiple tests that are using the invocation counts. Documentation doesn't list the workaround for TGL but applying it fixes the tests. Signed-off-by: Tapani Pälli <tapani.palli@intel.com> --- drivers/gpu/drm/i915/gt/intel_workarounds.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+)