| Message ID | 20191106212636.502471-1-gwan-gyeong.mun@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/i915: Split a setting of MSA to MST and SST | expand |
On Wed, 2019-11-06 at 23:26 +0200, Gwan-gyeong Mun wrote: > The setting of MSA is done by the DDI .pre_enable() hook. And when we > are > using MST, the MSA is only set to first mst stream by calling of > DDI .pre_eanble() hook. It raies issues to non-first mst streams. > Wrong MSA or missed MSA packets might show scrambled screen or wrong > screen. > > This splits a setting of MSA to MST and SST cases. And In the MST > case it > will call a setting of MSA after an allocating of Virtual Channel > from > MST encoder pre_enable callback. Reviewed-by: José Roberto de Souza <jose.souza@intel.com> > > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> > Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=112212 > Fixes: 0c06fa156006 ("drm/i915/dp: Add support of BT.2020 Colorimetry > to DP MSA") > Fixes: d4a415dcda35 ("drm/i915: Fix MST oops due to MSA changes") > Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com> > --- > drivers/gpu/drm/i915/display/intel_ddi.c | 10 ++++++---- > drivers/gpu/drm/i915/display/intel_dp_mst.c | 3 +++ > 2 files changed, 9 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c > b/drivers/gpu/drm/i915/display/intel_ddi.c > index c91521bcf06a..ef41fa0f77f0 100644 > --- a/drivers/gpu/drm/i915/display/intel_ddi.c > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c > @@ -1794,10 +1794,8 @@ void intel_ddi_set_dp_msa(const struct > intel_crtc_state *crtc_state, > * of Color Encoding Format and Content Color Gamut] while > sending > * YCBCR 420, HDR BT.2020 signals we should program MSA MISC1 > fields > * which indicate VSC SDP for the Pixel Encoding/Colorimetry > Format. > - * > - * FIXME MST doesn't pass in the conn_state > */ > - if (conn_state && intel_dp_needs_vsc_sdp(crtc_state, > conn_state)) > + if (intel_dp_needs_vsc_sdp(crtc_state, conn_state)) > temp |= DP_MSA_MISC_COLOR_VSC_SDP; > > I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp); > @@ -3606,7 +3604,11 @@ static void intel_ddi_pre_enable_dp(struct > intel_encoder *encoder, > else > hsw_ddi_pre_enable_dp(encoder, crtc_state, conn_state); > > - intel_ddi_set_dp_msa(crtc_state, conn_state); > + /* MST will call a setting of MSA after an allocating of > Virtual Channel > + * from MST encoder pre_enable callback. > + */ > + if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) > + intel_ddi_set_dp_msa(crtc_state, conn_state); > } > > static void intel_ddi_pre_enable_hdmi(struct intel_encoder *encoder, > diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c > b/drivers/gpu/drm/i915/display/intel_dp_mst.c > index 5e267c5b4c20..cb77f8072820 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c > +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c > @@ -345,6 +345,9 @@ static void intel_mst_pre_enable_dp(struct > intel_encoder *encoder, > */ > if (INTEL_GEN(dev_priv) < 12 || !first_mst_stream) > intel_ddi_enable_pipe_clock(pipe_config); > + > + intel_ddi_set_dp_msa(pipe_config, conn_state); > + > } > > static void intel_mst_enable_dp(struct intel_encoder *encoder,
On Wed, Nov 06, 2019 at 11:26:36PM +0200, Gwan-gyeong Mun wrote: >The setting of MSA is done by the DDI .pre_enable() hook. And when we are >using MST, the MSA is only set to first mst stream by calling of >DDI .pre_eanble() hook. It raies issues to non-first mst streams. >Wrong MSA or missed MSA packets might show scrambled screen or wrong >screen. > >This splits a setting of MSA to MST and SST cases. And In the MST case it >will call a setting of MSA after an allocating of Virtual Channel from >MST encoder pre_enable callback. > >Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> >Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> >Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=112212 >Fixes: 0c06fa156006 ("drm/i915/dp: Add support of BT.2020 Colorimetry to DP MSA") >Fixes: d4a415dcda35 ("drm/i915: Fix MST oops due to MSA changes") >Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com> >--- > drivers/gpu/drm/i915/display/intel_ddi.c | 10 ++++++---- > drivers/gpu/drm/i915/display/intel_dp_mst.c | 3 +++ > 2 files changed, 9 insertions(+), 4 deletions(-) > >diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c >index c91521bcf06a..ef41fa0f77f0 100644 >--- a/drivers/gpu/drm/i915/display/intel_ddi.c >+++ b/drivers/gpu/drm/i915/display/intel_ddi.c >@@ -1794,10 +1794,8 @@ void intel_ddi_set_dp_msa(const struct intel_crtc_state *crtc_state, > * of Color Encoding Format and Content Color Gamut] while sending > * YCBCR 420, HDR BT.2020 signals we should program MSA MISC1 fields > * which indicate VSC SDP for the Pixel Encoding/Colorimetry Format. >- * >- * FIXME MST doesn't pass in the conn_state > */ >- if (conn_state && intel_dp_needs_vsc_sdp(crtc_state, conn_state)) >+ if (intel_dp_needs_vsc_sdp(crtc_state, conn_state)) > temp |= DP_MSA_MISC_COLOR_VSC_SDP; > > I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp); >@@ -3606,7 +3604,11 @@ static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder, > else > hsw_ddi_pre_enable_dp(encoder, crtc_state, conn_state); > >- intel_ddi_set_dp_msa(crtc_state, conn_state); >+ /* MST will call a setting of MSA after an allocating of Virtual Channel >+ * from MST encoder pre_enable callback. >+ */ >+ if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) >+ intel_ddi_set_dp_msa(crtc_state, conn_state); > } > > static void intel_ddi_pre_enable_hdmi(struct intel_encoder *encoder, >diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c >index 5e267c5b4c20..cb77f8072820 100644 >--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c >+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c >@@ -345,6 +345,9 @@ static void intel_mst_pre_enable_dp(struct intel_encoder *encoder, > */ > if (INTEL_GEN(dev_priv) < 12 || !first_mst_stream) > intel_ddi_enable_pipe_clock(pipe_config); >+ >+ intel_ddi_set_dp_msa(pipe_config, conn_state); >+ extra new line here, otherwise Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Lucas De Marchi > } > > static void intel_mst_enable_dp(struct intel_encoder *encoder, >-- >2.23.0 > >_______________________________________________ >Intel-gfx mailing list >Intel-gfx@lists.freedesktop.org >https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Hi, > -----Original Message----- > From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Souza, > Jose > Sent: torstai 7. marraskuuta 2019 23.16 > To: Mun, Gwan-gyeong <gwan-gyeong.mun@intel.com>; intel- > gfx@lists.freedesktop.org > Subject: Re: [Intel-gfx] [PATCH] drm/i915: Split a setting of MSA to MST and SST > > On Wed, 2019-11-06 at 23:26 +0200, Gwan-gyeong Mun wrote: > > The setting of MSA is done by the DDI .pre_enable() hook. And when we > > are using MST, the MSA is only set to first mst stream by calling of > > DDI .pre_eanble() hook. It raies issues to non-first mst streams. > > Wrong MSA or missed MSA packets might show scrambled screen or wrong > > screen. > > > > This splits a setting of MSA to MST and SST cases. And In the MST case > > it will call a setting of MSA after an allocating of Virtual Channel > > from MST encoder pre_enable callback. > > Reviewed-by: José Roberto de Souza <jose.souza@intel.com> Also Tested-by: Jani Saarinen <jani.saarinen@intel.com> On Dell XPS without patch even booting with console (runlevel 3) screen black on second monitor after DP MST monitor. Dell XPS (KBL) > TypeC-to DP tp Dell 4K MST monitor and from that to DP monitor (Dell) and this last in the chain black. But with patched kernel screen visible. GG, is issues seen in Shards real or can this be merged now? > > > > > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> > > Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=112212 > > Fixes: 0c06fa156006 ("drm/i915/dp: Add support of BT.2020 Colorimetry > > to DP MSA") > > Fixes: d4a415dcda35 ("drm/i915: Fix MST oops due to MSA changes") > > Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com> > > --- > > drivers/gpu/drm/i915/display/intel_ddi.c | 10 ++++++---- > > drivers/gpu/drm/i915/display/intel_dp_mst.c | 3 +++ > > 2 files changed, 9 insertions(+), 4 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c > > b/drivers/gpu/drm/i915/display/intel_ddi.c > > index c91521bcf06a..ef41fa0f77f0 100644 > > --- a/drivers/gpu/drm/i915/display/intel_ddi.c > > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c > > @@ -1794,10 +1794,8 @@ void intel_ddi_set_dp_msa(const struct > > intel_crtc_state *crtc_state, > > * of Color Encoding Format and Content Color Gamut] while > sending > > * YCBCR 420, HDR BT.2020 signals we should program MSA MISC1 > fields > > * which indicate VSC SDP for the Pixel Encoding/Colorimetry > Format. > > - * > > - * FIXME MST doesn't pass in the conn_state > > */ > > - if (conn_state && intel_dp_needs_vsc_sdp(crtc_state, > > conn_state)) > > + if (intel_dp_needs_vsc_sdp(crtc_state, conn_state)) > > temp |= DP_MSA_MISC_COLOR_VSC_SDP; > > > > I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp); @@ - > 3606,7 > > +3604,11 @@ static void intel_ddi_pre_enable_dp(struct intel_encoder > > *encoder, > > else > > hsw_ddi_pre_enable_dp(encoder, crtc_state, > conn_state); > > > > - intel_ddi_set_dp_msa(crtc_state, conn_state); > > + /* MST will call a setting of MSA after an allocating of > > Virtual Channel > > + * from MST encoder pre_enable callback. > > + */ > > + if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) > > + intel_ddi_set_dp_msa(crtc_state, conn_state); > > } > > > > static void intel_ddi_pre_enable_hdmi(struct intel_encoder *encoder, > > diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c > > b/drivers/gpu/drm/i915/display/intel_dp_mst.c > > index 5e267c5b4c20..cb77f8072820 100644 > > --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c > > +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c > > @@ -345,6 +345,9 @@ static void intel_mst_pre_enable_dp(struct > > intel_encoder *encoder, > > */ > > if (INTEL_GEN(dev_priv) < 12 || !first_mst_stream) > > intel_ddi_enable_pipe_clock(pipe_config); > > + > > + intel_ddi_set_dp_msa(pipe_config, conn_state); > > + > > } > > > > static void intel_mst_enable_dp(struct intel_encoder *encoder, > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
On Thu, Nov 07, 2019 at 03:22:33PM -0800, Lucas De Marchi wrote: > On Wed, Nov 06, 2019 at 11:26:36PM +0200, Gwan-gyeong Mun wrote: > >The setting of MSA is done by the DDI .pre_enable() hook. And when we are > >using MST, the MSA is only set to first mst stream by calling of > >DDI .pre_eanble() hook. It raies issues to non-first mst streams. > >Wrong MSA or missed MSA packets might show scrambled screen or wrong > >screen. > > > >This splits a setting of MSA to MST and SST cases. And In the MST case it > >will call a setting of MSA after an allocating of Virtual Channel from > >MST encoder pre_enable callback. > > > >Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> > >Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> > >Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=112212 > >Fixes: 0c06fa156006 ("drm/i915/dp: Add support of BT.2020 Colorimetry to DP MSA") > >Fixes: d4a415dcda35 ("drm/i915: Fix MST oops due to MSA changes") > >Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com> > >--- > > drivers/gpu/drm/i915/display/intel_ddi.c | 10 ++++++---- > > drivers/gpu/drm/i915/display/intel_dp_mst.c | 3 +++ > > 2 files changed, 9 insertions(+), 4 deletions(-) > > > >diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c > >index c91521bcf06a..ef41fa0f77f0 100644 > >--- a/drivers/gpu/drm/i915/display/intel_ddi.c > >+++ b/drivers/gpu/drm/i915/display/intel_ddi.c > >@@ -1794,10 +1794,8 @@ void intel_ddi_set_dp_msa(const struct intel_crtc_state *crtc_state, > > * of Color Encoding Format and Content Color Gamut] while sending > > * YCBCR 420, HDR BT.2020 signals we should program MSA MISC1 fields > > * which indicate VSC SDP for the Pixel Encoding/Colorimetry Format. > >- * > >- * FIXME MST doesn't pass in the conn_state > > */ > >- if (conn_state && intel_dp_needs_vsc_sdp(crtc_state, conn_state)) > >+ if (intel_dp_needs_vsc_sdp(crtc_state, conn_state)) > > temp |= DP_MSA_MISC_COLOR_VSC_SDP; > > > > I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp); > >@@ -3606,7 +3604,11 @@ static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder, > > else > > hsw_ddi_pre_enable_dp(encoder, crtc_state, conn_state); > > > >- intel_ddi_set_dp_msa(crtc_state, conn_state); > >+ /* MST will call a setting of MSA after an allocating of Virtual Channel > >+ * from MST encoder pre_enable callback. > >+ */ > >+ if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) > >+ intel_ddi_set_dp_msa(crtc_state, conn_state); > > } > > > > static void intel_ddi_pre_enable_hdmi(struct intel_encoder *encoder, > >diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c > >index 5e267c5b4c20..cb77f8072820 100644 > >--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c > >+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c > >@@ -345,6 +345,9 @@ static void intel_mst_pre_enable_dp(struct intel_encoder *encoder, > > */ > > if (INTEL_GEN(dev_priv) < 12 || !first_mst_stream) > > intel_ddi_enable_pipe_clock(pipe_config); > >+ > >+ intel_ddi_set_dp_msa(pipe_config, conn_state); > >+ > > extra new line here, otherwise Nuked while pushing to dinq. Thanks for the patch and review. > > > Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> > > Lucas De Marchi > > > } > > > > static void intel_mst_enable_dp(struct intel_encoder *encoder, > >-- > >2.23.0 > > > >_______________________________________________ > >Intel-gfx mailing list > >Intel-gfx@lists.freedesktop.org > >https://lists.freedesktop.org/mailman/listinfo/intel-gfx > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
On Sat, 2019-11-09 at 05:16 +0000, Patchwork wrote: > == Series Details == > > Series: drm/i915: Split a setting of MSA to MST and SST (rev3) > URL : https://patchwork.freedesktop.org/series/69092/ > State : failure > > == Summary == > > CI Bug Log - changes from CI_DRM_7288_full -> Patchwork_15183_full > ==================================================== > > Summary > ------- > > **FAILURE** > > Serious unknown changes coming with Patchwork_15183_full absolutely > need to be > verified manually. > > If you think the reported changes have nothing to do with the > changes > introduced in Patchwork_15183_full, please notify your bug team to > allow them > to document this new failure mode, which will reduce false > positives in CI. > > > > Possible new issues > ------------------- > > Here are the unknown changes that may have been introduced in > Patchwork_15183_full: > > ### IGT changes ### > > #### Possible regressions #### > > * igt@kms_flip@modeset-vs-vblank-race: > - shard-glk: [PASS][1] -> [FAIL][2] > [1]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-glk2/igt@kms_flip@modeset-vs-vblank-race.html This report was false positive result. The result showed as Starting subtest: modeset-vs-vblank-race Subtest modeset-vs-vblank-race: SUCCESS (13.947s) > [2]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15183/shard-glk3/igt@kms_flip@modeset-vs-vblank-race.html The error message was (kms_flip:1114) INFO: Beginning modeset-vs-vblank-race on pipe C, connector HDMI-A-2 (kms_flip:1114) CRITICAL: Failed assertion: end - start > 0.9 * actual_frame_time(o) && end - start < 2.6 * actual_frame_time(o) This patch is not related to HDMI connector case, it only affects DP connecot (SST, MST). There fore this error is not related the patch. > > > Known issues > ------------ > > Here are the changes found in Patchwork_15183_full that come from > known issues: > > ### IGT changes ### > > #### Issues hit #### > > * igt@gem_ctx_isolation@bcs0-s3: > - shard-tglb: [PASS][3] -> [INCOMPLETE][4] ([fdo#111832]) > [3]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-tglb9/igt@gem_ctx_isolation@bcs0-s3.html > [4]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15183/shard-tglb1/igt@gem_ctx_isolation@bcs0-s3.html > > * igt@gem_ctx_persistence@rcs0-mixed-process: > - shard-apl: [PASS][5] -> [FAIL][6] ([fdo#112194]) > [5]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-apl4/igt@gem_ctx_persistence@rcs0-mixed-process.html > [6]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15183/shard-apl7/igt@gem_ctx_persistence@rcs0-mixed-process.html > > * igt@gem_ctx_persistence@vcs1-queued: > - shard-iclb: [PASS][7] -> [SKIP][8] ([fdo#109276] / > [fdo#112080]) +5 similar issues > [7]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-iclb4/igt@gem_ctx_persistence@vcs1-queued.html > [8]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15183/shard-iclb7/igt@gem_ctx_persistence@vcs1-queued.html > > * igt@gem_exec_nop@basic-series: > - shard-tglb: [PASS][9] -> [INCOMPLETE][10] > ([fdo#111747]) > [9]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-tglb3/igt@gem_exec_nop@basic-series.html > [10]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15183/shard-tglb6/igt@gem_exec_nop@basic-series.html > > * igt@gem_exec_parallel@contexts: > - shard-tglb: [PASS][11] -> [INCOMPLETE][12] > ([fdo#111867]) > [11]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-tglb2/igt@gem_exec_parallel@contexts.html > [12]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15183/shard-tglb6/igt@gem_exec_parallel@contexts.html > > * igt@gem_exec_parallel@vcs1-fds: > - shard-iclb: [PASS][13] -> [SKIP][14] ([fdo#112080]) +17 > similar issues > [13]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-iclb4/igt@gem_exec_parallel@vcs1-fds.html > [14]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15183/shard-iclb7/igt@gem_exec_parallel@vcs1-fds.html > > * igt@gem_exec_schedule@preempt-queue-bsd: > - shard-iclb: [PASS][15] -> [SKIP][16] ([fdo#112146]) +6 > similar issues > [15]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-iclb7/igt@gem_exec_schedule@preempt-queue-bsd.html > [16]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15183/shard-iclb4/igt@gem_exec_schedule@preempt-queue-bsd.html > > * igt@gem_exec_schedule@preempt-queue-contexts-chain-bsd2: > - shard-tglb: [PASS][17] -> [INCOMPLETE][18] > ([fdo#111677]) > [17]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-tglb2/igt@gem_exec_schedule@preempt-queue-contexts-chain-bsd2.html > [18]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15183/shard-tglb6/igt@gem_exec_schedule@preempt-queue-contexts-chain-bsd2.html > > * igt@gem_userptr_blits@sync-unmap: > - shard-hsw: [PASS][19] -> [DMESG-WARN][20] > ([fdo#110789] / [fdo#111870]) > [19]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-hsw6/igt@gem_userptr_blits@sync-unmap.html > [20]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15183/shard-hsw1/igt@gem_userptr_blits@sync-unmap.html > > * igt@gem_userptr_blits@sync-unmap-after-close: > - shard-snb: [PASS][21] -> [DMESG-WARN][22] > ([fdo#110789] / [fdo#111870]) > [21]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-snb1/igt@gem_userptr_blits@sync-unmap-after-close.html > [22]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15183/shard-snb6/igt@gem_userptr_blits@sync-unmap-after-close.html > > * igt@i915_pm_dc@dc5-dpms: > - shard-iclb: [PASS][23] -> [FAIL][24] ([fdo#111795 ]) > [23]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-iclb1/igt@i915_pm_dc@dc5-dpms.html > [24]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15183/shard-iclb3/igt@i915_pm_dc@dc5-dpms.html > > * igt@i915_pm_dc@dc6-psr: > - shard-iclb: [PASS][25] -> [FAIL][26] ([fdo#110548]) > [25]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-iclb2/igt@i915_pm_dc@dc6-psr.html > [26]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15183/shard-iclb4/igt@i915_pm_dc@dc6-psr.html > > * igt@i915_selftest@mock_requests: > - shard-skl: [PASS][27] -> [INCOMPLETE][28] > ([fdo#108972]) > [27]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-skl4/igt@i915_selftest@mock_requests.html > [28]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15183/shard-skl6/igt@i915_selftest@mock_requests.html > > * igt@i915_suspend@fence-restore-tiled2untiled: > - shard-tglb: [PASS][29] -> [INCOMPLETE][30] > ([fdo#111832] / [fdo#111850]) +4 similar issues > [29]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-tglb1/igt@i915_suspend@fence-restore-tiled2untiled.html > [30]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15183/shard-tglb3/igt@i915_suspend@fence-restore-tiled2untiled.html > > * igt@kms_fbcon_fbt@fbc-suspend: > - shard-tglb: [PASS][31] -> [INCOMPLETE][32] > ([fdo#111747] / [fdo#111832] / [fdo#111850]) > [31]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-tglb9/igt@kms_fbcon_fbt@fbc-suspend.html > [32]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15183/shard-tglb3/igt@kms_fbcon_fbt@fbc-suspend.html > > * igt@kms_flip@2x-flip-vs-suspend-interruptible: > - shard-hsw: [PASS][33] -> [INCOMPLETE][34] > ([fdo#103540]) > [33]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-hsw5/igt@kms_flip@2x-flip-vs-suspend-interruptible.html > [34]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15183/shard-hsw5/igt@kms_flip@2x-flip-vs-suspend-interruptible.html > > * igt@kms_flip@flip-vs-expired-vblank-interruptible: > - shard-skl: [PASS][35] -> [FAIL][36] ([fdo#105363]) > [35]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-skl6/igt@kms_flip@flip-vs-expired-vblank-interruptible.html > [36]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15183/shard-skl4/igt@kms_flip@flip-vs-expired-vblank-interruptible.html > > * igt@kms_flip@flip-vs-suspend-interruptible: > - shard-apl: [PASS][37] -> [DMESG-WARN][38] > ([fdo#108566]) +2 similar issues > [37]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-apl8/igt@kms_flip@flip-vs-suspend-interruptible.html > [38]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15183/shard-apl6/igt@kms_flip@flip-vs-suspend-interruptible.html > > * igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-blt: > - shard-iclb: [PASS][39] -> [FAIL][40] ([fdo#103167]) +2 > similar issues > [39]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-iclb7/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-blt.html > [40]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15183/shard-iclb2/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-blt.html > > * igt@kms_frontbuffer_tracking@fbc-suspend: > - shard-iclb: [PASS][41] -> [INCOMPLETE][42] > ([fdo#107713]) > [41]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-iclb3/igt@kms_frontbuffer_tracking@fbc-suspend.html > [42]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15183/shard-iclb4/igt@kms_frontbuffer_tracking@fbc-suspend.html > > * igt@kms_frontbuffer_tracking@fbcpsr-1p-pri-indfb-multidraw: > - shard-tglb: [PASS][43] -> [FAIL][44] ([fdo#103167]) +2 > similar issues > [43]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-tglb4/igt@kms_frontbuffer_tracking@fbcpsr-1p-pri-indfb-multidraw.html > [44]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15183/shard-tglb7/igt@kms_frontbuffer_tracking@fbcpsr-1p-pri-indfb-multidraw.html > > * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a: > - shard-kbl: [PASS][45] -> [DMESG-WARN][46] > ([fdo#108566]) +1 similar issue > [45]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-kbl3/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html > [46]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15183/shard-kbl4/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html > > * igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min: > - shard-skl: [PASS][47] -> [FAIL][48] ([fdo#108145]) > [47]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-skl9/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html > [48]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15183/shard-skl1/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html > > * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc: > - shard-skl: [PASS][49] -> [FAIL][50] ([fdo#108145] / > [fdo#110403]) > [49]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-skl8/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html > [50]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15183/shard-skl10/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html > > * igt@kms_psr@psr2_cursor_render: > - shard-iclb: [PASS][51] -> [SKIP][52] ([fdo#109441]) +1 > similar issue > [51]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-iclb2/igt@kms_psr@psr2_cursor_render.html > [52]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15183/shard-iclb4/igt@kms_psr@psr2_cursor_render.html > > * igt@kms_vblank@pipe-b-ts-continuation-dpms-suspend: > - shard-tglb: [PASS][53] -> [INCOMPLETE][54] > ([fdo#111850]) > [53]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-tglb4/igt@kms_vblank@pipe-b-ts-continuation-dpms-suspend.html > [54]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15183/shard-tglb5/igt@kms_vblank@pipe-b-ts-continuation-dpms-suspend.html > > * igt@prime_busy@hang-bsd2: > - shard-iclb: [PASS][55] -> [SKIP][56] ([fdo#109276]) +20 > similar issues > [55]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-iclb4/igt@prime_busy@hang-bsd2.html > [56]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15183/shard-iclb7/igt@prime_busy@hang-bsd2.html > > > #### Possible fixes #### > > * igt@gem_ctx_persistence@bcs0-mixed-process: > - shard-skl: [FAIL][57] ([fdo#112194]) -> [PASS][58] > [57]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-skl8/igt@gem_ctx_persistence@bcs0-mixed-process.html > [58]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15183/shard-skl10/igt@gem_ctx_persistence@bcs0-mixed-process.html > > * igt@gem_ctx_persistence@vcs1-mixed-process: > - shard-iclb: [SKIP][59] ([fdo#109276] / [fdo#112080]) -> > [PASS][60] +3 similar issues > [59]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-iclb6/igt@gem_ctx_persistence@vcs1-mixed-process.html > [60]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15183/shard-iclb2/igt@gem_ctx_persistence@vcs1-mixed-process.html > > * igt@gem_ctx_shared@exec-single-timeline-bsd: > - shard-iclb: [SKIP][61] ([fdo#110841]) -> [PASS][62] > [61]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-iclb1/igt@gem_ctx_shared@exec-single-timeline-bsd.html > [62]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15183/shard-iclb3/igt@gem_ctx_shared@exec-single-timeline-bsd.html > > * igt@gem_ctx_switch@vcs1-heavy-queue: > - shard-iclb: [SKIP][63] ([fdo#112080]) -> [PASS][64] +9 > similar issues > [63]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-iclb5/igt@gem_ctx_switch@vcs1-heavy-queue.html > [64]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15183/shard-iclb1/igt@gem_ctx_switch@vcs1-heavy-queue.html > > * igt@gem_eio@in-flight-suspend: > - shard-tglb: [INCOMPLETE][65] ([fdo#111832] / > [fdo#111850] / [fdo#112081]) -> [PASS][66] > [65]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-tglb8/igt@gem_eio@in-flight-suspend.html > [66]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15183/shard-tglb7/igt@gem_eio@in-flight-suspend.html > > * igt@gem_exec_balancer@smoke: > - shard-iclb: [SKIP][67] ([fdo#110854]) -> [PASS][68] > [67]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-iclb3/igt@gem_exec_balancer@smoke.html > [68]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15183/shard-iclb4/igt@gem_exec_balancer@smoke.html > > * igt@gem_exec_create@basic: > - shard-tglb: [INCOMPLETE][69] ([fdo#111736]) -> > [PASS][70] > [69]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-tglb6/igt@gem_exec_create@basic.html > [70]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15183/shard-tglb9/igt@gem_exec_create@basic.html > > * igt@gem_exec_schedule@preempt-contexts-bsd2: > - shard-iclb: [SKIP][71] ([fdo#109276]) -> [PASS][72] +20 > similar issues > [71]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-iclb5/igt@gem_exec_schedule@preempt-contexts-bsd2.html > [72]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15183/shard-iclb1/igt@gem_exec_schedule@preempt-contexts-bsd2.html > > * igt@gem_exec_schedule@preempt-queue-contexts-blt: > - shard-tglb: [INCOMPLETE][73] ([fdo#111606] / > [fdo#111677]) -> [PASS][74] > [73]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-tglb6/igt@gem_exec_schedule@preempt-queue-contexts-blt.html > [74]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15183/shard-tglb2/igt@gem_exec_schedule@preempt-queue-contexts-blt.html > > * igt@gem_exec_schedule@preemptive-hang-bsd: > - shard-iclb: [SKIP][75] ([fdo#112146]) -> [PASS][76] +6 > similar issues > [75]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-iclb2/igt@gem_exec_schedule@preemptive-hang-bsd.html > [76]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15183/shard-iclb5/igt@gem_exec_schedule@preemptive-hang-bsd.html > > * igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy: > - shard-hsw: [DMESG-WARN][77] ([fdo#111870]) -> > [PASS][78] > [77]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-hsw7/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy.html > [78]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15183/shard-hsw2/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy.html > > * igt@gem_workarounds@suspend-resume: > - shard-kbl: [DMESG-WARN][79] ([fdo#103313]) -> > [PASS][80] > [79]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-kbl4/igt@gem_workarounds@suspend-resume.html > [80]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15183/shard-kbl3/igt@gem_workarounds@suspend-resume.html > > * igt@i915_pm_rpm@system-suspend: > - shard-tglb: [INCOMPLETE][81] ([fdo#111747] / > [fdo#111850]) -> [PASS][82] > [81]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-tglb3/igt@i915_pm_rpm@system-suspend.html > [82]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15183/shard-tglb2/igt@i915_pm_rpm@system-suspend.html > > * igt@i915_selftest@live_hangcheck: > - shard-snb: [INCOMPLETE][83] ([fdo#105411]) -> > [PASS][84] > [83]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-snb4/igt@i915_selftest@live_hangcheck.html > [84]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15183/shard-snb6/igt@i915_selftest@live_hangcheck.html > > * igt@i915_suspend@sysfs-reader: > - shard-apl: [DMESG-WARN][85] ([fdo#108566]) -> > [PASS][86] +1 similar issue > [85]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-apl6/igt@i915_suspend@sysfs-reader.html > [86]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15183/shard-apl4/igt@i915_suspend@sysfs-reader.html > > * igt@kms_atomic_transition@plane-all-modeset-transition: > - shard-hsw: [DMESG-WARN][87] ([fdo#102614]) -> > [PASS][88] > [87]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-hsw5/igt@kms_atomic_transition@plane-all-modeset-transition.html > [88]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15183/shard-hsw8/igt@kms_atomic_transition@plane-all-modeset-transition.html > > * igt@kms_color@pipe-a-gamma: > - shard-skl: [FAIL][89] ([fdo#104782]) -> [PASS][90] > [89]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-skl4/igt@kms_color@pipe-a-gamma.html > [90]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15183/shard-skl6/igt@kms_color@pipe-a-gamma.html > > * igt@kms_cursor_crc@pipe-a-cursor-128x128-offscreen: > - shard-skl: [FAIL][91] ([fdo#103232]) -> [PASS][92] > [91]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-skl4/igt@kms_cursor_crc@pipe-a-cursor-128x128-offscreen.html > [92]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15183/shard-skl6/igt@kms_cursor_crc@pipe-a-cursor-128x128-offscreen.html > > * igt@kms_draw_crc@draw-method-rgb565-mmap-gtt-untiled: > - shard-skl: [FAIL][93] ([fdo#103184] / [fdo#103232]) -> > [PASS][94] +1 similar issue > [93]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-skl4/igt@kms_draw_crc@draw-method-rgb565-mmap-gtt-untiled.html > [94]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15183/shard-skl6/igt@kms_draw_crc@draw-method-rgb565-mmap-gtt-untiled.html > > * igt@kms_frontbuffer_tracking@fbc-suspend: > - shard-kbl: [DMESG-WARN][95] ([fdo#108566]) -> > [PASS][96] +9 similar issues > [95]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-kbl7/igt@kms_frontbuffer_tracking@fbc-suspend.html > [96]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15183/shard-kbl2/igt@kms_frontbuffer_tracking@fbc-suspend.html > > * igt@kms_frontbuffer_tracking@fbc-tilingchange: > - shard-tglb: [FAIL][97] ([fdo#103167]) -> [PASS][98] > [97]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-tglb7/igt@kms_frontbuffer_tracking@fbc-tilingchange.html > [98]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15183/shard-tglb8/igt@kms_frontbuffer_tracking@fbc-tilingchange.html > > * igt@kms > _frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-pwrite: > - shard-iclb: [FAIL][99] ([fdo#103167]) -> [PASS][100] +6 > similar issues > [99]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-iclb6/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-pwrite.html > [100]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15183/shard-iclb2/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-pwrite.html > > * igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-blt: > - shard-skl: [FAIL][101] ([fdo#103167]) -> [PASS][102] > [101]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-skl4/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-blt.html > [102]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15183/shard-skl6/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-blt.html > > * igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence: > - shard-skl: [FAIL][103] ([fdo#103191]) -> [PASS][104] > [103]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-skl4/igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence.html > [104]: https://intel-gfx-ci.01.org/tree/dr > > == Logs == > > For more details see: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15183/index.html
On Mon, 2019-11-11 at 11:46 +0000, Saarinen, Jani wrote: > Hi, > > > -----Original Message----- > > From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf > > Of Souza, > > Jose > > Sent: torstai 7. marraskuuta 2019 23.16 > > To: Mun, Gwan-gyeong <gwan-gyeong.mun@intel.com>; intel- > > gfx@lists.freedesktop.org > > Subject: Re: [Intel-gfx] [PATCH] drm/i915: Split a setting of MSA > > to MST and SST > > > > On Wed, 2019-11-06 at 23:26 +0200, Gwan-gyeong Mun wrote: > > > The setting of MSA is done by the DDI .pre_enable() hook. And > > > when we > > > are using MST, the MSA is only set to first mst stream by calling > > > of > > > DDI .pre_eanble() hook. It raies issues to non-first mst streams. > > > Wrong MSA or missed MSA packets might show scrambled screen or > > > wrong > > > screen. > > > > > > This splits a setting of MSA to MST and SST cases. And In the MST > > > case > > > it will call a setting of MSA after an allocating of Virtual > > > Channel > > > from MST encoder pre_enable callback. > > > > Reviewed-by: José Roberto de Souza <jose.souza@intel.com> > Also Tested-by: Jani Saarinen <jani.saarinen@intel.com> > On Dell XPS without patch even booting with console (runlevel 3) > screen black on second monitor after DP MST monitor. > Dell XPS (KBL) > TypeC-to DP tp Dell 4K MST monitor and from that to > DP monitor (Dell) and this last in the chain black. > But with patched kernel screen visible. > > GG, is issues seen in Shards real or can this be merged now? Hi Jani Saarinen, IMHO, the reported possible regression seemed not related to this patch. I commented and replied to the regression report mail of Rev 3. Jani N, if you are available, could you review and merge the patch? Br, G.G. > > > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> > > > Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> > > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=112212 > > > Fixes: 0c06fa156006 ("drm/i915/dp: Add support of BT.2020 > > > Colorimetry > > > to DP MSA") > > > Fixes: d4a415dcda35 ("drm/i915: Fix MST oops due to MSA changes") > > > Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com> > > > --- > > > drivers/gpu/drm/i915/display/intel_ddi.c | 10 ++++++---- > > > drivers/gpu/drm/i915/display/intel_dp_mst.c | 3 +++ > > > 2 files changed, 9 insertions(+), 4 deletions(-) > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c > > > b/drivers/gpu/drm/i915/display/intel_ddi.c > > > index c91521bcf06a..ef41fa0f77f0 100644 > > > --- a/drivers/gpu/drm/i915/display/intel_ddi.c > > > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c > > > @@ -1794,10 +1794,8 @@ void intel_ddi_set_dp_msa(const struct > > > intel_crtc_state *crtc_state, > > > * of Color Encoding Format and Content Color Gamut] while > > sending > > > * YCBCR 420, HDR BT.2020 signals we should program MSA MISC1 > > fields > > > * which indicate VSC SDP for the Pixel Encoding/Colorimetry > > Format. > > > - * > > > - * FIXME MST doesn't pass in the conn_state > > > */ > > > - if (conn_state && intel_dp_needs_vsc_sdp(crtc_state, > > > conn_state)) > > > + if (intel_dp_needs_vsc_sdp(crtc_state, conn_state)) > > > temp |= DP_MSA_MISC_COLOR_VSC_SDP; > > > > > > I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp); @@ - > > 3606,7 > > > +3604,11 @@ static void intel_ddi_pre_enable_dp(struct > > > intel_encoder > > > *encoder, > > > else > > > hsw_ddi_pre_enable_dp(encoder, crtc_state, > > conn_state); > > > - intel_ddi_set_dp_msa(crtc_state, conn_state); > > > + /* MST will call a setting of MSA after an allocating of > > > Virtual Channel > > > + * from MST encoder pre_enable callback. > > > + */ > > > + if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) > > > + intel_ddi_set_dp_msa(crtc_state, conn_state); > > > } > > > > > > static void intel_ddi_pre_enable_hdmi(struct intel_encoder > > > *encoder, > > > diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c > > > b/drivers/gpu/drm/i915/display/intel_dp_mst.c > > > index 5e267c5b4c20..cb77f8072820 100644 > > > --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c > > > +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c > > > @@ -345,6 +345,9 @@ static void intel_mst_pre_enable_dp(struct > > > intel_encoder *encoder, > > > */ > > > if (INTEL_GEN(dev_priv) < 12 || !first_mst_stream) > > > intel_ddi_enable_pipe_clock(pipe_config); > > > + > > > + intel_ddi_set_dp_msa(pipe_config, conn_state); > > > + > > > } > > > > > > static void intel_mst_enable_dp(struct intel_encoder *encoder, > > _______________________________________________ > > Intel-gfx mailing list > > Intel-gfx@lists.freedesktop.org > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Hi, > -----Original Message----- > From: Mun, Gwan-gyeong <gwan-gyeong.mun@intel.com> > Sent: maanantai 11. marraskuuta 2019 17.04 > To: Saarinen, Jani <jani.saarinen@intel.com>; Nikula, Jani <jani.nikula@intel.com>; > intel-gfx@lists.freedesktop.org; Souza, Jose <jose.souza@intel.com> > Subject: Re: [Intel-gfx] [PATCH] drm/i915: Split a setting of MSA to MST and SST > > On Mon, 2019-11-11 at 11:46 +0000, Saarinen, Jani wrote: > > Hi, > > > > > -----Original Message----- > > > From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf > > > Of Souza, Jose > > > Sent: torstai 7. marraskuuta 2019 23.16 > > > To: Mun, Gwan-gyeong <gwan-gyeong.mun@intel.com>; intel- > > > gfx@lists.freedesktop.org > > > Subject: Re: [Intel-gfx] [PATCH] drm/i915: Split a setting of MSA to > > > MST and SST > > > > > > On Wed, 2019-11-06 at 23:26 +0200, Gwan-gyeong Mun wrote: > > > > The setting of MSA is done by the DDI .pre_enable() hook. And when > > > > we are using MST, the MSA is only set to first mst stream by > > > > calling of DDI .pre_eanble() hook. It raies issues to non-first > > > > mst streams. > > > > Wrong MSA or missed MSA packets might show scrambled screen or > > > > wrong screen. > > > > > > > > This splits a setting of MSA to MST and SST cases. And In the MST > > > > case it will call a setting of MSA after an allocating of Virtual > > > > Channel from MST encoder pre_enable callback. > > > > > > Reviewed-by: José Roberto de Souza <jose.souza@intel.com> > > Also Tested-by: Jani Saarinen <jani.saarinen@intel.com> On Dell XPS > > without patch even booting with console (runlevel 3) screen black on > > second monitor after DP MST monitor. > > Dell XPS (KBL) > TypeC-to DP tp Dell 4K MST monitor and from that to > > DP monitor (Dell) and this last in the chain black. > > But with patched kernel screen visible. > > > > GG, is issues seen in Shards real or can this be merged now? > Hi Jani Saarinen, > IMHO, the reported possible regression seemed not related to this patch. > I commented and replied to the regression report mail of Rev 3. > > Jani N, if you are available, could you review and merge the patch? Ville already did
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index c91521bcf06a..ef41fa0f77f0 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -1794,10 +1794,8 @@ void intel_ddi_set_dp_msa(const struct intel_crtc_state *crtc_state, * of Color Encoding Format and Content Color Gamut] while sending * YCBCR 420, HDR BT.2020 signals we should program MSA MISC1 fields * which indicate VSC SDP for the Pixel Encoding/Colorimetry Format. - * - * FIXME MST doesn't pass in the conn_state */ - if (conn_state && intel_dp_needs_vsc_sdp(crtc_state, conn_state)) + if (intel_dp_needs_vsc_sdp(crtc_state, conn_state)) temp |= DP_MSA_MISC_COLOR_VSC_SDP; I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp); @@ -3606,7 +3604,11 @@ static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder, else hsw_ddi_pre_enable_dp(encoder, crtc_state, conn_state); - intel_ddi_set_dp_msa(crtc_state, conn_state); + /* MST will call a setting of MSA after an allocating of Virtual Channel + * from MST encoder pre_enable callback. + */ + if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) + intel_ddi_set_dp_msa(crtc_state, conn_state); } static void intel_ddi_pre_enable_hdmi(struct intel_encoder *encoder, diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index 5e267c5b4c20..cb77f8072820 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -345,6 +345,9 @@ static void intel_mst_pre_enable_dp(struct intel_encoder *encoder, */ if (INTEL_GEN(dev_priv) < 12 || !first_mst_stream) intel_ddi_enable_pipe_clock(pipe_config); + + intel_ddi_set_dp_msa(pipe_config, conn_state); + } static void intel_mst_enable_dp(struct intel_encoder *encoder,
The setting of MSA is done by the DDI .pre_enable() hook. And when we are using MST, the MSA is only set to first mst stream by calling of DDI .pre_eanble() hook. It raies issues to non-first mst streams. Wrong MSA or missed MSA packets might show scrambled screen or wrong screen. This splits a setting of MSA to MST and SST cases. And In the MST case it will call a setting of MSA after an allocating of Virtual Channel from MST encoder pre_enable callback. Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=112212 Fixes: 0c06fa156006 ("drm/i915/dp: Add support of BT.2020 Colorimetry to DP MSA") Fixes: d4a415dcda35 ("drm/i915: Fix MST oops due to MSA changes") Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com> --- drivers/gpu/drm/i915/display/intel_ddi.c | 10 ++++++---- drivers/gpu/drm/i915/display/intel_dp_mst.c | 3 +++ 2 files changed, 9 insertions(+), 4 deletions(-)