| Message ID | 20191111111029.9126-3-vandita.kulkarni@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add support for mipi dsi cmd mode | expand |
On Mon, 11 Nov 2019, Vandita Kulkarni <vandita.kulkarni@intel.com> wrote: > Configure the transcoder to operate in TE GATE command mode > and take TE events from GPIO. > Also disable the periodic command mode, that GOP would have > programmed. > > Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com> > --- > drivers/gpu/drm/i915/display/icl_dsi.c | 36 ++++++++++++++++++++++++++ > 1 file changed, 36 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c > index 8eb2d7f29c82..5ff2a1ffd3ea 100644 > --- a/drivers/gpu/drm/i915/display/icl_dsi.c > +++ b/drivers/gpu/drm/i915/display/icl_dsi.c > @@ -704,6 +704,10 @@ gen11_dsi_configure_transcoder(struct intel_encoder *encoder, > tmp |= VIDEO_MODE_SYNC_PULSE; > break; > } > + } else { > + tmp &= ~OP_MODE_MASK; > + tmp |= CMD_MODE_TE_GATE; > + tmp |= TE_SOURCE_GPIO; Do we have TE source specified in VBT or somewhere? I can live with this *for now* but it does freak me out a bit that we might also be using the utility pin for backlight PWM output. That would conflict magnificently. Maybe at least add a FIXME comment about that? > } > > I915_WRITE(DSI_TRANS_FUNC_CONF(dsi_trans), tmp); > @@ -953,6 +957,26 @@ static void gen11_dsi_setup_timeouts(struct intel_encoder *encoder) > } > } > > +static void gen11_dsi_config_util_pin(struct intel_encoder *encoder) > +{ > + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > + struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); > + u32 tmp; > + > + /* > + * used as TE i/p for DSI0, > + * for dual link/DSI1 TE is from slave DSI1 > + * through GPIO. > + */ > + if (is_vid_mode(intel_dsi) || (intel_dsi->ports & BIT(PORT_B))) > + return; > + > + tmp = I915_READ(UTIL_PIN_CTL); > + tmp |= UTIL_PIN_DIRECTION_INPUT; > + tmp |= UTIL_PIN_ENABLE; > + I915_WRITE(UTIL_PIN_CTL, tmp); You'll also need to disable the utility pin somewhere, else you'll get warnings from assert_can_enable_dc6(). > +} > + > static void > gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder, > const struct intel_crtc_state *pipe_config) > @@ -974,6 +998,9 @@ gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder, > /* setup D-PHY timings */ > gen11_dsi_setup_dphy_timings(encoder); > > + /* Since transcoder is configured to take events from GPIO */ > + gen11_dsi_config_util_pin(encoder); > + > /* step 4h: setup DSI protocol timeouts */ > gen11_dsi_setup_timeouts(encoder); > > @@ -1104,6 +1131,15 @@ static void gen11_dsi_deconfigure_trancoder(struct intel_encoder *encoder) > enum transcoder dsi_trans; > u32 tmp; > > + /* disable periodic update mode */ > + if (is_cmd_mode(intel_dsi)) { > + for_each_dsi_port(port, intel_dsi->ports) { > + tmp = I915_READ(DSI_CMD_FRMCTL(port)); > + tmp &= ~DSI_PERIODIC_FRAME_UPDATE_ENABLE; > + I915_WRITE(DSI_CMD_FRMCTL(port), tmp); > + } > + } > + > /* put dsi link in ULPS */ > for_each_dsi_port(port, intel_dsi->ports) { > dsi_trans = dsi_port_to_transcoder(port);
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c index 8eb2d7f29c82..5ff2a1ffd3ea 100644 --- a/drivers/gpu/drm/i915/display/icl_dsi.c +++ b/drivers/gpu/drm/i915/display/icl_dsi.c @@ -704,6 +704,10 @@ gen11_dsi_configure_transcoder(struct intel_encoder *encoder, tmp |= VIDEO_MODE_SYNC_PULSE; break; } + } else { + tmp &= ~OP_MODE_MASK; + tmp |= CMD_MODE_TE_GATE; + tmp |= TE_SOURCE_GPIO; } I915_WRITE(DSI_TRANS_FUNC_CONF(dsi_trans), tmp); @@ -953,6 +957,26 @@ static void gen11_dsi_setup_timeouts(struct intel_encoder *encoder) } } +static void gen11_dsi_config_util_pin(struct intel_encoder *encoder) +{ + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); + u32 tmp; + + /* + * used as TE i/p for DSI0, + * for dual link/DSI1 TE is from slave DSI1 + * through GPIO. + */ + if (is_vid_mode(intel_dsi) || (intel_dsi->ports & BIT(PORT_B))) + return; + + tmp = I915_READ(UTIL_PIN_CTL); + tmp |= UTIL_PIN_DIRECTION_INPUT; + tmp |= UTIL_PIN_ENABLE; + I915_WRITE(UTIL_PIN_CTL, tmp); +} + static void gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder, const struct intel_crtc_state *pipe_config) @@ -974,6 +998,9 @@ gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder, /* setup D-PHY timings */ gen11_dsi_setup_dphy_timings(encoder); + /* Since transcoder is configured to take events from GPIO */ + gen11_dsi_config_util_pin(encoder); + /* step 4h: setup DSI protocol timeouts */ gen11_dsi_setup_timeouts(encoder); @@ -1104,6 +1131,15 @@ static void gen11_dsi_deconfigure_trancoder(struct intel_encoder *encoder) enum transcoder dsi_trans; u32 tmp; + /* disable periodic update mode */ + if (is_cmd_mode(intel_dsi)) { + for_each_dsi_port(port, intel_dsi->ports) { + tmp = I915_READ(DSI_CMD_FRMCTL(port)); + tmp &= ~DSI_PERIODIC_FRAME_UPDATE_ENABLE; + I915_WRITE(DSI_CMD_FRMCTL(port), tmp); + } + } + /* put dsi link in ULPS */ for_each_dsi_port(port, intel_dsi->ports) { dsi_trans = dsi_port_to_transcoder(port);
Configure the transcoder to operate in TE GATE command mode and take TE events from GPIO. Also disable the periodic command mode, that GOP would have programmed. Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com> --- drivers/gpu/drm/i915/display/icl_dsi.c | 36 ++++++++++++++++++++++++++ 1 file changed, 36 insertions(+)