| Message ID | 20191126002635.5779-6-radhakrishna.sripada@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Clear Color Support for TGL Render Decompression | expand |
On Mon, Nov 25, 2019 at 04:26:33PM -0800, Radhakrishna Sripada wrote: > From: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> > > intel_fill_fb_info() has grown quite large and wrapping the offset checks > into a separate function makes the loop a bit easier to follow. > > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> > Cc: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com> > Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> > --- > drivers/gpu/drm/i915/display/intel_display.c | 69 ++++++++++++-------- > 1 file changed, 40 insertions(+), 29 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c > index 1ef1988b9e12..6c4274c1564d 100644 > --- a/drivers/gpu/drm/i915/display/intel_display.c > +++ b/drivers/gpu/drm/i915/display/intel_display.c > @@ -2742,6 +2742,43 @@ static bool intel_plane_needs_remap(const struct intel_plane_state *plane_state) > return stride > max_stride; > } > > +static int > +intel_fb_check_ccs_xy(struct drm_framebuffer *fb, int x, int y) > +{ > + struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); > + int hsub = fb->format->hsub; > + int vsub = fb->format->vsub; > + int tile_width, tile_height; > + int ccs_x, ccs_y; > + int main_x, main_y; > + > + intel_tile_dims(fb, 1, &tile_width, &tile_height); > + > + tile_width *= hsub; > + tile_height *= vsub; > + > + ccs_x = (x * hsub) % tile_width; > + ccs_y = (y * vsub) % tile_height; > + main_x = intel_fb->normal[0].x % tile_width; > + main_y = intel_fb->normal[0].y % tile_height; > + > + /* > + * CCS doesn't have its own x/y offset register, so the intra CCS tile > + * x/y offsets must match between CCS and the main surface. > + */ > + if (main_x != ccs_x || main_y != ccs_y) { > + DRM_DEBUG_KMS("Bad CCS x/y (main %d,%d ccs %d,%d) full (main %d,%d ccs %d,%d)\n", > + main_x, main_y, > + ccs_x, ccs_y, > + intel_fb->normal[0].x, > + intel_fb->normal[0].y, > + x, y); > + return -EINVAL; > + } > + > + return 0; > +} > + > static int > intel_fill_fb_info(struct drm_i915_private *dev_priv, > struct drm_framebuffer *fb) > @@ -2773,35 +2810,9 @@ intel_fill_fb_info(struct drm_i915_private *dev_priv, > } > > if (is_ccs_modifier(fb->modifier) && i == 1) { > - int hsub = fb->format->hsub; > - int vsub = fb->format->vsub; > - int tile_width, tile_height; > - int main_x, main_y; > - int ccs_x, ccs_y; > - > - intel_tile_dims(fb, i, &tile_width, &tile_height); > - > - tile_width *= hsub; > - tile_height *= vsub; > - > - ccs_x = (x * hsub) % tile_width; > - ccs_y = (y * vsub) % tile_height; > - main_x = intel_fb->normal[0].x % tile_width; > - main_y = intel_fb->normal[0].y % tile_height; > - > - /* > - * CCS doesn't have its own x/y offset register, so the intra CCS tile > - * x/y offsets must match between CCS and the main surface. > - */ > - if (main_x != ccs_x || main_y != ccs_y) { > - DRM_DEBUG_KMS("Bad CCS x/y (main %d,%d ccs %d,%d) full (main %d,%d ccs %d,%d)\n", > - main_x, main_y, > - ccs_x, ccs_y, > - intel_fb->normal[0].x, > - intel_fb->normal[0].y, > - x, y); > - return -EINVAL; > - } > + ret = intel_fb_check_ccs_xy(fb, x, y); > + if (ret) > + return ret; > } > > /* > -- > 2.20.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 1ef1988b9e12..6c4274c1564d 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -2742,6 +2742,43 @@ static bool intel_plane_needs_remap(const struct intel_plane_state *plane_state) return stride > max_stride; } +static int +intel_fb_check_ccs_xy(struct drm_framebuffer *fb, int x, int y) +{ + struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); + int hsub = fb->format->hsub; + int vsub = fb->format->vsub; + int tile_width, tile_height; + int ccs_x, ccs_y; + int main_x, main_y; + + intel_tile_dims(fb, 1, &tile_width, &tile_height); + + tile_width *= hsub; + tile_height *= vsub; + + ccs_x = (x * hsub) % tile_width; + ccs_y = (y * vsub) % tile_height; + main_x = intel_fb->normal[0].x % tile_width; + main_y = intel_fb->normal[0].y % tile_height; + + /* + * CCS doesn't have its own x/y offset register, so the intra CCS tile + * x/y offsets must match between CCS and the main surface. + */ + if (main_x != ccs_x || main_y != ccs_y) { + DRM_DEBUG_KMS("Bad CCS x/y (main %d,%d ccs %d,%d) full (main %d,%d ccs %d,%d)\n", + main_x, main_y, + ccs_x, ccs_y, + intel_fb->normal[0].x, + intel_fb->normal[0].y, + x, y); + return -EINVAL; + } + + return 0; +} + static int intel_fill_fb_info(struct drm_i915_private *dev_priv, struct drm_framebuffer *fb) @@ -2773,35 +2810,9 @@ intel_fill_fb_info(struct drm_i915_private *dev_priv, } if (is_ccs_modifier(fb->modifier) && i == 1) { - int hsub = fb->format->hsub; - int vsub = fb->format->vsub; - int tile_width, tile_height; - int main_x, main_y; - int ccs_x, ccs_y; - - intel_tile_dims(fb, i, &tile_width, &tile_height); - - tile_width *= hsub; - tile_height *= vsub; - - ccs_x = (x * hsub) % tile_width; - ccs_y = (y * vsub) % tile_height; - main_x = intel_fb->normal[0].x % tile_width; - main_y = intel_fb->normal[0].y % tile_height; - - /* - * CCS doesn't have its own x/y offset register, so the intra CCS tile - * x/y offsets must match between CCS and the main surface. - */ - if (main_x != ccs_x || main_y != ccs_y) { - DRM_DEBUG_KMS("Bad CCS x/y (main %d,%d ccs %d,%d) full (main %d,%d ccs %d,%d)\n", - main_x, main_y, - ccs_x, ccs_y, - intel_fb->normal[0].x, - intel_fb->normal[0].y, - x, y); - return -EINVAL; - } + ret = intel_fb_check_ccs_xy(fb, x, y); + if (ret) + return ret; } /*