@@ -421,6 +421,25 @@ extern "C" {
*/
#define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS fourcc_mod_code(INTEL, 6)
+/*
+ * Intel Color Control Surface with Clear Color (CCS) for Gen-12 render
+ * compression.
+ *
+ * The main surface is Y-tiled and is at plane index 0 whereas CCS is linear
+ * and at index 1. The clear color is stored at index 2, and the pitch should
+ * be ignored. The clear color structure is 256 bits. The first 128 bits
+ * represents Raw Clear Color Red, Green, Blue and Alpha color each represented
+ * by 32 bits. The 3D engine can use the raw clear color and the surface format
+ * to generate a converted clear color of size 64 bits. The first 32 bits store
+ * the Lower Converted Clear Color value and the next 32 bits store the Higher
+ * Converted Clear Color value when applicable. The Converted Clear Color values
+ * are consumed by the DE. The last 64 bits are used to store Color Discard
+ * Enable and Depth Clear Value Valid which are ignored by the DE. A CCS cache
+ * line corresponds to an area of 4x1 tiles in the main surface. The main
+ * surface pitch is required to be a multiple of 4 tile widths.
+ */
+#define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC fourcc_mod_code(INTEL, 8)
+
/*
* Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
*