| Message ID | 20200129224206.10577-1-anusha.srivatsa@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/i915/tgl: Implement Wa_1606931601 | expand |
On Wed, Jan 29, 2020 at 02:42:06PM -0800, Anusha Srivatsa wrote: > Disable Inter and intra Read Suppression (bit 15) and > Early Read and Src Swap (bit 14) by setting the chicken > register. > > BSpec: 46045,52890 > > v2: Follow the Bspec implementation for the WA. > v3: Have 2 separate defines for bit 14 and 15. > - Rename register definitions with TGL_ prefix The hardware guys changed their mind again and we're back to only needing bit 14 now. They updated the bspec and the underlying database yet again. :-/ > > Cc: Matt Roper <matthew.d.roper@intel.com> > Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com> > --- > drivers/gpu/drm/i915/gt/intel_workarounds.c | 6 ++++++ > drivers/gpu/drm/i915/i915_reg.h | 2 ++ > 2 files changed, 8 insertions(+) > > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c > index 5a7db279f702..1f84cd595f88 100644 > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c > @@ -593,6 +593,12 @@ static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine, > wa_add(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK, val, > IS_TGL_REVID(engine->i915, TGL_REVID_A0, TGL_REVID_A0) ? 0 : > FF_MODE2_TDS_TIMER_MASK); > + > + /* Wa_1606931601:tgl */ > + WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2, > + GEN12_EARLY_READ_SRC0_DISABLE | > + GEN12_INTER_INTRA_READ_SUPPRESSION_DISABLE); I think Daniele already mentioned this on the other discussion, but ROW_CHICKEN2 isn't part of the context image on gen12 (see bspec page 46255). This is a change from ICL where it *was* part of the context (see bspec page 18907), so even though we handled this register in the ctx_workarounds_init for ICL, that's not the appropriate place to put it for TGL. Since this isn't a context workaround, we need to determine whether it's a general GT workaround (which would be initialized in tgl_gt_workarounds_init) or an engine workaround (which would be initialized in {rcs,xcs}_engine_wa_init. In this case the register we're modifying is 0xe49c; according to bspec page 52078 this falls in one of the forcewake ranges listed under the render engine column (0E000-0E8FF). So I believe in this case that means we want to update rcs_engine_wa_init() with this workaround --- that ensures that the workaround will be re-applied any time the engine is reset (even if it's not a full-GPU reset). Matt > + > } > > static void > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 4c72b8ac0f2e..70ead809c706 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -9149,6 +9149,8 @@ enum { > #define DOP_CLOCK_GATING_DISABLE (1 << 0) > #define PUSH_CONSTANT_DEREF_DISABLE (1 << 8) > #define GEN11_TDL_CLOCK_GATING_FIX_DISABLE (1 << 1) > +#define GEN12_EARLY_READ_SRC0_DISABLE (1 << 14) > +#define GEN12_INTER_INTRA_READ_SUPPRESSION_DISABLE (1 << 15) > > #define HSW_ROW_CHICKEN3 _MMIO(0xe49c) > #define HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE (1 << 6) > -- > 2.25.0 >
> -----Original Message----- > From: Roper, Matthew D <matthew.d.roper@intel.com> > Sent: Thursday, January 30, 2020 12:43 PM > To: Srivatsa, Anusha <anusha.srivatsa@intel.com> > Cc: intel-gfx@lists.freedesktop.org; Ceraolo Spurio, Daniele > <daniele.ceraolospurio@intel.com> > Subject: Re: [PATCH] drm/i915/tgl: Implement Wa_1606931601 > > On Wed, Jan 29, 2020 at 02:42:06PM -0800, Anusha Srivatsa wrote: > > Disable Inter and intra Read Suppression (bit 15) and Early Read and > > Src Swap (bit 14) by setting the chicken register. > > > > BSpec: 46045,52890 > > > > v2: Follow the Bspec implementation for the WA. > > v3: Have 2 separate defines for bit 14 and 15. > > - Rename register definitions with TGL_ prefix > > The hardware guys changed their mind again and we're back to only needing > bit 14 now. They updated the bspec and the underlying database yet again. > :-/ ☹ > > > > Cc: Matt Roper <matthew.d.roper@intel.com> > > Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com> > > --- > > drivers/gpu/drm/i915/gt/intel_workarounds.c | 6 ++++++ > > drivers/gpu/drm/i915/i915_reg.h | 2 ++ > > 2 files changed, 8 insertions(+) > > > > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c > > b/drivers/gpu/drm/i915/gt/intel_workarounds.c > > index 5a7db279f702..1f84cd595f88 100644 > > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c > > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c > > @@ -593,6 +593,12 @@ static void tgl_ctx_workarounds_init(struct > intel_engine_cs *engine, > > wa_add(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK, val, > > IS_TGL_REVID(engine->i915, TGL_REVID_A0, TGL_REVID_A0) ? 0 : > > FF_MODE2_TDS_TIMER_MASK); > > + > > + /* Wa_1606931601:tgl */ > > + WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2, > > + GEN12_EARLY_READ_SRC0_DISABLE | > > + > GEN12_INTER_INTRA_READ_SUPPRESSION_DISABLE); > > I think Daniele already mentioned this on the other discussion, but > ROW_CHICKEN2 isn't part of the context image on gen12 (see bspec page > 46255). This is a change from ICL where it *was* part of the context (see > bspec page 18907), so even though we handled this register in the > ctx_workarounds_init for ICL, that's not the appropriate place to put it for > TGL. Agreed. > Since this isn't a context workaround, we need to determine whether it's a > general GT workaround (which would be initialized in > tgl_gt_workarounds_init) or an engine workaround (which would be > initialized in {rcs,xcs}_engine_wa_init. In this case the register we're > modifying is 0xe49c; according to bspec page 52078 this falls in one of the > forcewake ranges listed under the render engine column (0E000-0E8FF). The register we are setting is 0xe4f4. This comes under Render engine. Adding this change to rcs_engine_wa_init(). > So I > believe in this case that means we want to update > rcs_engine_wa_init() with this workaround --- that ensures that the > workaround will be re-applied any time the engine is reset (even if it's not a > full-GPU reset). Yes. Adding this to rcs_engine_wa_init(). Anusha > > Matt > > > + > > } > > > > static void > > diff --git a/drivers/gpu/drm/i915/i915_reg.h > > b/drivers/gpu/drm/i915/i915_reg.h index 4c72b8ac0f2e..70ead809c706 > > 100644 > > --- a/drivers/gpu/drm/i915/i915_reg.h > > +++ b/drivers/gpu/drm/i915/i915_reg.h > > @@ -9149,6 +9149,8 @@ enum { > > #define DOP_CLOCK_GATING_DISABLE (1 << 0) > > #define PUSH_CONSTANT_DEREF_DISABLE (1 << 8) > > #define GEN11_TDL_CLOCK_GATING_FIX_DISABLE (1 << 1) > > +#define GEN12_EARLY_READ_SRC0_DISABLE (1 << 14) > > +#define GEN12_INTER_INTRA_READ_SUPPRESSION_DISABLE (1 << > 15) > > > > #define HSW_ROW_CHICKEN3 _MMIO(0xe49c) > > #define HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE (1 << 6) > > -- > > 2.25.0 > > > > -- > Matt Roper > Graphics Software Engineer > VTT-OSGC Platform Enablement > Intel Corporation > (916) 356-2795
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index 5a7db279f702..1f84cd595f88 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -593,6 +593,12 @@ static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine, wa_add(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK, val, IS_TGL_REVID(engine->i915, TGL_REVID_A0, TGL_REVID_A0) ? 0 : FF_MODE2_TDS_TIMER_MASK); + + /* Wa_1606931601:tgl */ + WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2, + GEN12_EARLY_READ_SRC0_DISABLE | + GEN12_INTER_INTRA_READ_SUPPRESSION_DISABLE); + } static void diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 4c72b8ac0f2e..70ead809c706 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -9149,6 +9149,8 @@ enum { #define DOP_CLOCK_GATING_DISABLE (1 << 0) #define PUSH_CONSTANT_DEREF_DISABLE (1 << 8) #define GEN11_TDL_CLOCK_GATING_FIX_DISABLE (1 << 1) +#define GEN12_EARLY_READ_SRC0_DISABLE (1 << 14) +#define GEN12_INTER_INTRA_READ_SUPPRESSION_DISABLE (1 << 15) #define HSW_ROW_CHICKEN3 _MMIO(0xe49c) #define HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE (1 << 6)
Disable Inter and intra Read Suppression (bit 15) and Early Read and Src Swap (bit 14) by setting the chicken register. BSpec: 46045,52890 v2: Follow the Bspec implementation for the WA. v3: Have 2 separate defines for bit 14 and 15. - Rename register definitions with TGL_ prefix Cc: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com> --- drivers/gpu/drm/i915/gt/intel_workarounds.c | 6 ++++++ drivers/gpu/drm/i915/i915_reg.h | 2 ++ 2 files changed, 8 insertions(+)