From patchwork Thu Apr 9 15:47:20 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Stanislav Lisovskiy X-Patchwork-Id: 11481947 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 5533117D4 for ; Thu, 9 Apr 2020 15:51:11 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 3D25420769 for ; Thu, 9 Apr 2020 15:51:11 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 3D25420769 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 928FC6EBF2; Thu, 9 Apr 2020 15:51:10 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTPS id CBD206EBF6 for ; Thu, 9 Apr 2020 15:51:09 +0000 (UTC) IronPort-SDR: C6GtJrMghJt6J7cF+Ty4fan8LAS9rWtnMDFs+jJiofqdOr53+la/M0KQjE9amej4wiifL8GlYr 9dHgzktrMWiA== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Apr 2020 08:51:09 -0700 IronPort-SDR: sjTvaLjFMSfG4912k4A0Aj7YslBL0ZEzCU0Emh5y82d2F4lA9IuAIOFKRcTjijrf2O36dvxNG+ LXLQrVCaCeqA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.72,363,1580803200"; d="scan'208";a="257857084" Received: from unknown (HELO slisovsk-Lenovo-ideapad-720S-13IKB.fi.intel.com) ([10.237.72.89]) by orsmga008.jf.intel.com with ESMTP; 09 Apr 2020 08:51:07 -0700 From: Stanislav Lisovskiy To: intel-gfx@lists.freedesktop.org Date: Thu, 9 Apr 2020 18:47:20 +0300 Message-Id: <20200409154730.18568-4-stanislav.lisovskiy@intel.com> X-Mailer: git-send-email 2.24.1.485.gad05a3d8e5 In-Reply-To: <20200409154730.18568-1-stanislav.lisovskiy@intel.com> References: <20200409154730.18568-1-stanislav.lisovskiy@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v22 03/13] drm/i915: Introduce skl_plane_wm_level accessor. X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jani.nikula@intel.com Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" For future Gen12 SAGV implementation we need to seemlessly alter wm levels calculated, depending on whether we are allowed to enable SAGV or not. So this accessor will give additional flexibility to do that. Currently this accessor is still simply working as "pass-through" function. This will be changed in next coming patches from this series. v2: - plane_id -> plane->id(Ville Syrjälä) - Moved wm_level var to have more local scope (Ville Syrjälä) - Renamed yuv to color_plane(Ville Syrjälä) in skl_plane_wm_level v3: - plane->id -> plane_id(this time for real, Ville Syrjälä) - Changed colorplane id type from boolean to int as index (Ville Syrjälä) - Moved crtc_state param so that it is first now (Ville Syrjälä) - Moved wm_level declaration to tigher scope in skl_write_plane_wm(Ville Syrjälä) v4: - Started to use enum values for color plane - Do sizeof for a type what we are memset'ing - Zero out wm_uv as well(Ville Syrjälä) Signed-off-by: Stanislav Lisovskiy --- drivers/gpu/drm/i915/intel_pm.c | 85 ++++++++++++++++++++++++++------- 1 file changed, 67 insertions(+), 18 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 176a28d71822..15ad6a73e0bd 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -4549,6 +4549,18 @@ icl_get_total_relative_data_rate(struct intel_crtc_state *crtc_state, return total_data_rate; } +static const struct skl_wm_level * +skl_plane_wm_level(const struct intel_crtc_state *crtc_state, + enum plane_id plane_id, + int level, + enum color_plane color_plane) +{ + const struct skl_plane_wm *wm = + &crtc_state->wm.skl.optimal.planes[plane_id]; + + return color_plane == COLOR_PLANE_Y ? &wm->wm[level] : &wm->uv_wm[level]; +} + static int skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state) { @@ -4608,22 +4620,28 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state) */ for (level = ilk_wm_max_level(dev_priv); level >= 0; level--) { blocks = 0; + for_each_plane_id_on_crtc(crtc, plane_id) { - const struct skl_plane_wm *wm = - &crtc_state->wm.skl.optimal.planes[plane_id]; + const struct skl_wm_level *wm_level; + const struct skl_wm_level *wm_uv_level; + + wm_level = skl_plane_wm_level(crtc_state, plane_id, + level, COLOR_PLANE_Y); + wm_uv_level = skl_plane_wm_level(crtc_state, plane_id, + level, COLOR_PLANE_UV); if (plane_id == PLANE_CURSOR) { - if (wm->wm[level].min_ddb_alloc > total[PLANE_CURSOR]) { + if (wm_level->min_ddb_alloc > total[PLANE_CURSOR]) { drm_WARN_ON(&dev_priv->drm, - wm->wm[level].min_ddb_alloc != U16_MAX); + wm_level->min_ddb_alloc != U16_MAX); blocks = U32_MAX; break; } continue; } - blocks += wm->wm[level].min_ddb_alloc; - blocks += wm->uv_wm[level].min_ddb_alloc; + blocks += wm_level->min_ddb_alloc; + blocks += wm_uv_level->min_ddb_alloc; } if (blocks <= alloc_size) { @@ -4646,11 +4664,16 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state) * proportional to its relative data rate. */ for_each_plane_id_on_crtc(crtc, plane_id) { - const struct skl_plane_wm *wm = - &crtc_state->wm.skl.optimal.planes[plane_id]; + const struct skl_wm_level *wm_level; + const struct skl_wm_level *wm_uv_level; u64 rate; u16 extra; + wm_level = skl_plane_wm_level(crtc_state, plane_id, + level, COLOR_PLANE_Y); + wm_uv_level = skl_plane_wm_level(crtc_state, plane_id, + level, COLOR_PLANE_UV); + if (plane_id == PLANE_CURSOR) continue; @@ -4665,7 +4688,7 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state) extra = min_t(u16, alloc_size, DIV64_U64_ROUND_UP(alloc_size * rate, total_data_rate)); - total[plane_id] = wm->wm[level].min_ddb_alloc + extra; + total[plane_id] = wm_level->min_ddb_alloc + extra; alloc_size -= extra; total_data_rate -= rate; @@ -4676,7 +4699,7 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state) extra = min_t(u16, alloc_size, DIV64_U64_ROUND_UP(alloc_size * rate, total_data_rate)); - uv_total[plane_id] = wm->uv_wm[level].min_ddb_alloc + extra; + uv_total[plane_id] = wm_uv_level->min_ddb_alloc + extra; alloc_size -= extra; total_data_rate -= rate; } @@ -4719,9 +4742,16 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state) */ for (level++; level <= ilk_wm_max_level(dev_priv); level++) { for_each_plane_id_on_crtc(crtc, plane_id) { + const struct skl_wm_level *wm_level; + const struct skl_wm_level *wm_uv_level; struct skl_plane_wm *wm = &crtc_state->wm.skl.optimal.planes[plane_id]; + wm_level = skl_plane_wm_level(crtc_state, plane_id, + level, COLOR_PLANE_Y); + wm_uv_level = skl_plane_wm_level(crtc_state, plane_id, + level, COLOR_PLANE_UV); + /* * We only disable the watermarks for each plane if * they exceed the ddb allocation of said plane. This @@ -4734,9 +4764,13 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state) * planes must be enabled before the level will be used." * So this is actually safe to do. */ - if (wm->wm[level].min_ddb_alloc > total[plane_id] || - wm->uv_wm[level].min_ddb_alloc > uv_total[plane_id]) - memset(&wm->wm[level], 0, sizeof(wm->wm[level])); + if (wm_level->min_ddb_alloc > total[plane_id] || + wm_uv_level->min_ddb_alloc > uv_total[plane_id]) { + memset(&wm->wm[level], 0, + sizeof(wm->wm[level])); + memset(&wm->uv_wm[level], 0, + sizeof(wm->uv_wm[level])); + } /* * Wa_1408961008:icl, ehl @@ -4744,9 +4778,14 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state) */ if (IS_GEN(dev_priv, 11) && level == 1 && wm->wm[0].plane_en) { - wm->wm[level].plane_res_b = wm->wm[0].plane_res_b; - wm->wm[level].plane_res_l = wm->wm[0].plane_res_l; - wm->wm[level].ignore_lines = wm->wm[0].ignore_lines; + wm_level = skl_plane_wm_level(crtc_state, plane_id, + 0, COLOR_PLANE_Y); + wm->wm[level].plane_res_b = + wm_level->plane_res_b; + wm->wm[level].plane_res_l = + wm_level->plane_res_l; + wm->wm[level].ignore_lines = + wm_level->ignore_lines; } } } @@ -5360,8 +5399,13 @@ void skl_write_plane_wm(struct intel_plane *plane, &crtc_state->wm.skl.plane_ddb_uv[plane_id]; for (level = 0; level <= max_level; level++) { + const struct skl_wm_level *wm_level; + int color_plane = 0; + + wm_level = skl_plane_wm_level(crtc_state, plane_id, level, color_plane); + skl_write_wm_level(dev_priv, PLANE_WM(pipe, plane_id, level), - &wm->wm[level]); + wm_level); } skl_write_wm_level(dev_priv, PLANE_WM_TRANS(pipe, plane_id), &wm->trans_wm); @@ -5394,8 +5438,13 @@ void skl_write_cursor_wm(struct intel_plane *plane, &crtc_state->wm.skl.plane_ddb_y[plane_id]; for (level = 0; level <= max_level; level++) { + const struct skl_wm_level *wm_level; + int color_plane = 0; + + wm_level = skl_plane_wm_level(crtc_state, plane_id, level, color_plane); + skl_write_wm_level(dev_priv, CUR_WM(pipe, level), - &wm->wm[level]); + wm_level); } skl_write_wm_level(dev_priv, CUR_WM_TRANS(pipe), &wm->trans_wm);