| Message ID | 20200420094746.20409-2-karthik.b.s@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Asynchronous flip implementation for i915 | expand |
Em seg, 2020-04-20 às 15:17 +0530, Karthik B S escreveu: > Add enable/disable flip done functions and the flip done handler > function which handles the flip done interrupt. > > Enable the flip done interrupt in IER. > > Enable flip done function is called before writing the > surface address register as the write to this register triggers > the flip done interrupt > > Flip done handler is used to send the page flip event as soon as the > surface address is written as per the requirement of async flips. > The interrupt is disabled after the event is sent. > > v2: -Change function name from icl_* to skl_* (Paulo) > -Move flip handler to this patch (Paulo) > -Remove vblank_put() (Paulo) > -Enable flip done interrupt for gen9+ only (Paulo) > -Enable flip done interrupt in power_well_post_enable hook (Paulo) > -Removed the event check in flip done handler to handle async > flips without pageflip events. > > Signed-off-by: Karthik B S <karthik.b.s@intel.com> > --- > drivers/gpu/drm/i915/display/intel_display.c | 7 +++ > drivers/gpu/drm/i915/i915_irq.c | 51 ++++++++++++++++++++ > drivers/gpu/drm/i915/i915_irq.h | 2 + > 3 files changed, 60 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c > index bae1d89875d6..3ce80634d047 100644 > --- a/drivers/gpu/drm/i915/display/intel_display.c > +++ b/drivers/gpu/drm/i915/display/intel_display.c > @@ -15391,6 +15391,13 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state) > if (state->modeset) > icl_dbuf_slice_pre_update(state); > > + for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { > + if (new_crtc_state->uapi.async_flip) { > + skl_enable_flip_done(&crtc->base); > + break; > + } > + } > + > /* Now enable the clocks, plane, pipe, and connectors that we set up. */ > dev_priv->display.commit_modeset_enables(state); > > diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c > index 1502ab44f1a5..9b64ed78523e 100644 > --- a/drivers/gpu/drm/i915/i915_irq.c > +++ b/drivers/gpu/drm/i915/i915_irq.c > @@ -1253,6 +1253,22 @@ display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv, > u32 crc4) {} > #endif > > +static void flip_done_handler(struct drm_i915_private *dev_priv, > + unsigned int pipe) > +{ > + struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe); > + struct drm_crtc_state *crtc_state = crtc->base.state; > + struct drm_device *dev = &dev_priv->drm; > + unsigned long irqflags; > + > + spin_lock_irqsave(&dev->event_lock, irqflags); > + > + drm_crtc_send_vblank_event(&crtc->base, crtc_state->event); > + crtc_state->event = NULL; > + > + spin_unlock_irqrestore(&dev->event_lock, irqflags); > + skl_disable_flip_done(&crtc->base); I am trying to understand the code here but I'm not 100% confident, so my comments may be wrong. Please correct me if needed. Can you please elaborate on why we have to disable the interrupt from the interrupt handler? This looks racy to me, but I may be wrong, so an explanation would help. In my head this would be the ideal: - If the whole ioctl is blocked until we get the interrupt (which is what patch 04 suggests), then whatever is blocking waiting on the interrupt should enable+disable the interrupt (so no disable_flip_done here). - If the ioctl is not blocked, then isn't there a race risk in case user space finds a way to submit 2 ioctls before we get an interrupt? If no, why would this be impossible? Some sort of refcounting could help in this case. I'm also thinking in cases like alternating between flips requiring events and flips not requiring events. > +} > > static void hsw_pipe_crc_irq_handler(struct drm_i915_private *dev_priv, > enum pipe pipe) > @@ -2355,6 +2371,9 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl) > if (iir & GEN8_PIPE_VBLANK) > intel_handle_vblank(dev_priv, pipe); > > + if (iir & GEN9_PIPE_PLANE1_FLIP_DONE) > + flip_done_handler(dev_priv, pipe); > + > if (iir & GEN8_PIPE_CDCLK_CRC_DONE) > hsw_pipe_crc_irq_handler(dev_priv, pipe); > > @@ -2636,6 +2655,19 @@ int bdw_enable_vblank(struct drm_crtc *crtc) > return 0; > } > > +void skl_enable_flip_done(struct drm_crtc *crtc) > +{ > + struct drm_i915_private *dev_priv = to_i915(crtc->dev); > + enum pipe pipe = to_intel_crtc(crtc)->pipe; > + unsigned long irqflags; > + > + spin_lock_irqsave(&dev_priv->irq_lock, irqflags); > + > + bdw_enable_pipe_irq(dev_priv, pipe, GEN9_PIPE_PLANE1_FLIP_DONE); > + > + spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); > +} > + > /* Called from drm generic code, passed 'crtc' which > * we use as a pipe index > */ > @@ -2696,6 +2728,19 @@ void bdw_disable_vblank(struct drm_crtc *crtc) > spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); > } > > +void skl_disable_flip_done(struct drm_crtc *crtc) > +{ > + struct drm_i915_private *dev_priv = to_i915(crtc->dev); > + enum pipe pipe = to_intel_crtc(crtc)->pipe; > + unsigned long irqflags; > + > + spin_lock_irqsave(&dev_priv->irq_lock, irqflags); > + > + bdw_disable_pipe_irq(dev_priv, pipe, GEN9_PIPE_PLANE1_FLIP_DONE); > + > + spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); > +} > + > static void ibx_irq_reset(struct drm_i915_private *dev_priv) > { > struct intel_uncore *uncore = &dev_priv->uncore; > @@ -2893,6 +2938,9 @@ void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv, > u32 extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN; > enum pipe pipe; > > + if (INTEL_GEN(dev_priv) >= 9) > + extra_ier |= GEN9_PIPE_PLANE1_FLIP_DONE; > + > spin_lock_irq(&dev_priv->irq_lock); > > if (!intel_irqs_enabled(dev_priv)) { > @@ -3387,6 +3435,9 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv) > de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK | > GEN8_PIPE_FIFO_UNDERRUN; > > + if (INTEL_GEN(dev_priv) >= 9) > + de_pipe_enables |= GEN9_PIPE_PLANE1_FLIP_DONE; > + > de_port_enables = de_port_masked; > if (IS_GEN9_LP(dev_priv)) > de_port_enables |= BXT_DE_PORT_HOTPLUG_MASK; > diff --git a/drivers/gpu/drm/i915/i915_irq.h b/drivers/gpu/drm/i915/i915_irq.h > index 25f25cd95818..2f10c8135116 100644 > --- a/drivers/gpu/drm/i915/i915_irq.h > +++ b/drivers/gpu/drm/i915/i915_irq.h > @@ -112,11 +112,13 @@ int i915gm_enable_vblank(struct drm_crtc *crtc); > int i965_enable_vblank(struct drm_crtc *crtc); > int ilk_enable_vblank(struct drm_crtc *crtc); > int bdw_enable_vblank(struct drm_crtc *crtc); > +void skl_enable_flip_done(struct drm_crtc *crtc); > void i8xx_disable_vblank(struct drm_crtc *crtc); > void i915gm_disable_vblank(struct drm_crtc *crtc); > void i965_disable_vblank(struct drm_crtc *crtc); > void ilk_disable_vblank(struct drm_crtc *crtc); > void bdw_disable_vblank(struct drm_crtc *crtc); > +void skl_disable_flip_done(struct drm_crtc *crtc); > > void gen2_irq_reset(struct intel_uncore *uncore); > void gen3_irq_reset(struct intel_uncore *uncore, i915_reg_t imr,
On 4/24/2020 11:14 PM, Paulo Zanoni wrote: > Em seg, 2020-04-20 às 15:17 +0530, Karthik B S escreveu: >> Add enable/disable flip done functions and the flip done handler >> function which handles the flip done interrupt. >> >> Enable the flip done interrupt in IER. >> >> Enable flip done function is called before writing the >> surface address register as the write to this register triggers >> the flip done interrupt >> >> Flip done handler is used to send the page flip event as soon as the >> surface address is written as per the requirement of async flips. >> The interrupt is disabled after the event is sent. >> >> v2: -Change function name from icl_* to skl_* (Paulo) >> -Move flip handler to this patch (Paulo) >> -Remove vblank_put() (Paulo) >> -Enable flip done interrupt for gen9+ only (Paulo) >> -Enable flip done interrupt in power_well_post_enable hook (Paulo) >> -Removed the event check in flip done handler to handle async >> flips without pageflip events. >> >> Signed-off-by: Karthik B S <karthik.b.s@intel.com> >> --- >> drivers/gpu/drm/i915/display/intel_display.c | 7 +++ >> drivers/gpu/drm/i915/i915_irq.c | 51 ++++++++++++++++++++ >> drivers/gpu/drm/i915/i915_irq.h | 2 + >> 3 files changed, 60 insertions(+) >> >> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c >> index bae1d89875d6..3ce80634d047 100644 >> --- a/drivers/gpu/drm/i915/display/intel_display.c >> +++ b/drivers/gpu/drm/i915/display/intel_display.c >> @@ -15391,6 +15391,13 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state) >> if (state->modeset) >> icl_dbuf_slice_pre_update(state); >> >> + for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { >> + if (new_crtc_state->uapi.async_flip) { >> + skl_enable_flip_done(&crtc->base); >> + break; >> + } >> + } >> + >> /* Now enable the clocks, plane, pipe, and connectors that we set up. */ >> dev_priv->display.commit_modeset_enables(state); >> >> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c >> index 1502ab44f1a5..9b64ed78523e 100644 >> --- a/drivers/gpu/drm/i915/i915_irq.c >> +++ b/drivers/gpu/drm/i915/i915_irq.c >> @@ -1253,6 +1253,22 @@ display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv, >> u32 crc4) {} >> #endif >> >> +static void flip_done_handler(struct drm_i915_private *dev_priv, >> + unsigned int pipe) >> +{ >> + struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe); >> + struct drm_crtc_state *crtc_state = crtc->base.state; >> + struct drm_device *dev = &dev_priv->drm; >> + unsigned long irqflags; >> + >> + spin_lock_irqsave(&dev->event_lock, irqflags); >> + >> + drm_crtc_send_vblank_event(&crtc->base, crtc_state->event); >> + crtc_state->event = NULL; >> + >> + spin_unlock_irqrestore(&dev->event_lock, irqflags); >> + skl_disable_flip_done(&crtc->base); > > I am trying to understand the code here but I'm not 100% confident, so > my comments may be wrong. Please correct me if needed. > > Can you please elaborate on why we have to disable the interrupt from > the interrupt handler? This looks racy to me, but I may be wrong, so an > explanation would help. > > In my head this would be the ideal: > > - If the whole ioctl is blocked until we get the interrupt (which is > what patch 04 suggests), then whatever is blocking waiting on the > interrupt should enable+disable the interrupt (so no disable_flip_done > here). > > - If the ioctl is not blocked, then isn't there a race risk in case > user space finds a way to submit 2 ioctls before we get an interrupt? > If no, why would this be impossible? Some sort of refcounting could > help in this case. I'm also thinking in cases like alternating between > flips requiring events and flips not requiring events. > Agreed on this fully. My thinking was to just disable the interrupt soon after we've got it. But doing this in commit tail makes more sense, and especially now as I've made the call non blocking, it will definitely have a risk of being racy as you've mentioned. Moved this out of interrupt handler to intel_atomic_commit_tail function, where I'm disabling it after the wait for flip done. Thanks, Karthik.B.S >> +} >> >> static void hsw_pipe_crc_irq_handler(struct drm_i915_private *dev_priv, >> enum pipe pipe) >> @@ -2355,6 +2371,9 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl) >> if (iir & GEN8_PIPE_VBLANK) >> intel_handle_vblank(dev_priv, pipe); >> >> + if (iir & GEN9_PIPE_PLANE1_FLIP_DONE) >> + flip_done_handler(dev_priv, pipe); >> + >> if (iir & GEN8_PIPE_CDCLK_CRC_DONE) >> hsw_pipe_crc_irq_handler(dev_priv, pipe); >> >> @@ -2636,6 +2655,19 @@ int bdw_enable_vblank(struct drm_crtc *crtc) >> return 0; >> } >> >> +void skl_enable_flip_done(struct drm_crtc *crtc) >> +{ >> + struct drm_i915_private *dev_priv = to_i915(crtc->dev); >> + enum pipe pipe = to_intel_crtc(crtc)->pipe; >> + unsigned long irqflags; >> + >> + spin_lock_irqsave(&dev_priv->irq_lock, irqflags); >> + >> + bdw_enable_pipe_irq(dev_priv, pipe, GEN9_PIPE_PLANE1_FLIP_DONE); >> + >> + spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); >> +} >> + >> /* Called from drm generic code, passed 'crtc' which >> * we use as a pipe index >> */ >> @@ -2696,6 +2728,19 @@ void bdw_disable_vblank(struct drm_crtc *crtc) >> spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); >> } >> >> +void skl_disable_flip_done(struct drm_crtc *crtc) >> +{ >> + struct drm_i915_private *dev_priv = to_i915(crtc->dev); >> + enum pipe pipe = to_intel_crtc(crtc)->pipe; >> + unsigned long irqflags; >> + >> + spin_lock_irqsave(&dev_priv->irq_lock, irqflags); >> + >> + bdw_disable_pipe_irq(dev_priv, pipe, GEN9_PIPE_PLANE1_FLIP_DONE); >> + >> + spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); >> +} >> + >> static void ibx_irq_reset(struct drm_i915_private *dev_priv) >> { >> struct intel_uncore *uncore = &dev_priv->uncore; >> @@ -2893,6 +2938,9 @@ void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv, >> u32 extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN; >> enum pipe pipe; >> >> + if (INTEL_GEN(dev_priv) >= 9) >> + extra_ier |= GEN9_PIPE_PLANE1_FLIP_DONE; >> + >> spin_lock_irq(&dev_priv->irq_lock); >> >> if (!intel_irqs_enabled(dev_priv)) { >> @@ -3387,6 +3435,9 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv) >> de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK | >> GEN8_PIPE_FIFO_UNDERRUN; >> >> + if (INTEL_GEN(dev_priv) >= 9) >> + de_pipe_enables |= GEN9_PIPE_PLANE1_FLIP_DONE; >> + >> de_port_enables = de_port_masked; >> if (IS_GEN9_LP(dev_priv)) >> de_port_enables |= BXT_DE_PORT_HOTPLUG_MASK; >> diff --git a/drivers/gpu/drm/i915/i915_irq.h b/drivers/gpu/drm/i915/i915_irq.h >> index 25f25cd95818..2f10c8135116 100644 >> --- a/drivers/gpu/drm/i915/i915_irq.h >> +++ b/drivers/gpu/drm/i915/i915_irq.h >> @@ -112,11 +112,13 @@ int i915gm_enable_vblank(struct drm_crtc *crtc); >> int i965_enable_vblank(struct drm_crtc *crtc); >> int ilk_enable_vblank(struct drm_crtc *crtc); >> int bdw_enable_vblank(struct drm_crtc *crtc); >> +void skl_enable_flip_done(struct drm_crtc *crtc); >> void i8xx_disable_vblank(struct drm_crtc *crtc); >> void i915gm_disable_vblank(struct drm_crtc *crtc); >> void i965_disable_vblank(struct drm_crtc *crtc); >> void ilk_disable_vblank(struct drm_crtc *crtc); >> void bdw_disable_vblank(struct drm_crtc *crtc); >> +void skl_disable_flip_done(struct drm_crtc *crtc); >> >> void gen2_irq_reset(struct intel_uncore *uncore); >> void gen3_irq_reset(struct intel_uncore *uncore, i915_reg_t imr, >
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index bae1d89875d6..3ce80634d047 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -15391,6 +15391,13 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state) if (state->modeset) icl_dbuf_slice_pre_update(state); + for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { + if (new_crtc_state->uapi.async_flip) { + skl_enable_flip_done(&crtc->base); + break; + } + } + /* Now enable the clocks, plane, pipe, and connectors that we set up. */ dev_priv->display.commit_modeset_enables(state); diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 1502ab44f1a5..9b64ed78523e 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -1253,6 +1253,22 @@ display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv, u32 crc4) {} #endif +static void flip_done_handler(struct drm_i915_private *dev_priv, + unsigned int pipe) +{ + struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe); + struct drm_crtc_state *crtc_state = crtc->base.state; + struct drm_device *dev = &dev_priv->drm; + unsigned long irqflags; + + spin_lock_irqsave(&dev->event_lock, irqflags); + + drm_crtc_send_vblank_event(&crtc->base, crtc_state->event); + crtc_state->event = NULL; + + spin_unlock_irqrestore(&dev->event_lock, irqflags); + skl_disable_flip_done(&crtc->base); +} static void hsw_pipe_crc_irq_handler(struct drm_i915_private *dev_priv, enum pipe pipe) @@ -2355,6 +2371,9 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl) if (iir & GEN8_PIPE_VBLANK) intel_handle_vblank(dev_priv, pipe); + if (iir & GEN9_PIPE_PLANE1_FLIP_DONE) + flip_done_handler(dev_priv, pipe); + if (iir & GEN8_PIPE_CDCLK_CRC_DONE) hsw_pipe_crc_irq_handler(dev_priv, pipe); @@ -2636,6 +2655,19 @@ int bdw_enable_vblank(struct drm_crtc *crtc) return 0; } +void skl_enable_flip_done(struct drm_crtc *crtc) +{ + struct drm_i915_private *dev_priv = to_i915(crtc->dev); + enum pipe pipe = to_intel_crtc(crtc)->pipe; + unsigned long irqflags; + + spin_lock_irqsave(&dev_priv->irq_lock, irqflags); + + bdw_enable_pipe_irq(dev_priv, pipe, GEN9_PIPE_PLANE1_FLIP_DONE); + + spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); +} + /* Called from drm generic code, passed 'crtc' which * we use as a pipe index */ @@ -2696,6 +2728,19 @@ void bdw_disable_vblank(struct drm_crtc *crtc) spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); } +void skl_disable_flip_done(struct drm_crtc *crtc) +{ + struct drm_i915_private *dev_priv = to_i915(crtc->dev); + enum pipe pipe = to_intel_crtc(crtc)->pipe; + unsigned long irqflags; + + spin_lock_irqsave(&dev_priv->irq_lock, irqflags); + + bdw_disable_pipe_irq(dev_priv, pipe, GEN9_PIPE_PLANE1_FLIP_DONE); + + spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); +} + static void ibx_irq_reset(struct drm_i915_private *dev_priv) { struct intel_uncore *uncore = &dev_priv->uncore; @@ -2893,6 +2938,9 @@ void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv, u32 extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN; enum pipe pipe; + if (INTEL_GEN(dev_priv) >= 9) + extra_ier |= GEN9_PIPE_PLANE1_FLIP_DONE; + spin_lock_irq(&dev_priv->irq_lock); if (!intel_irqs_enabled(dev_priv)) { @@ -3387,6 +3435,9 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv) de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN; + if (INTEL_GEN(dev_priv) >= 9) + de_pipe_enables |= GEN9_PIPE_PLANE1_FLIP_DONE; + de_port_enables = de_port_masked; if (IS_GEN9_LP(dev_priv)) de_port_enables |= BXT_DE_PORT_HOTPLUG_MASK; diff --git a/drivers/gpu/drm/i915/i915_irq.h b/drivers/gpu/drm/i915/i915_irq.h index 25f25cd95818..2f10c8135116 100644 --- a/drivers/gpu/drm/i915/i915_irq.h +++ b/drivers/gpu/drm/i915/i915_irq.h @@ -112,11 +112,13 @@ int i915gm_enable_vblank(struct drm_crtc *crtc); int i965_enable_vblank(struct drm_crtc *crtc); int ilk_enable_vblank(struct drm_crtc *crtc); int bdw_enable_vblank(struct drm_crtc *crtc); +void skl_enable_flip_done(struct drm_crtc *crtc); void i8xx_disable_vblank(struct drm_crtc *crtc); void i915gm_disable_vblank(struct drm_crtc *crtc); void i965_disable_vblank(struct drm_crtc *crtc); void ilk_disable_vblank(struct drm_crtc *crtc); void bdw_disable_vblank(struct drm_crtc *crtc); +void skl_disable_flip_done(struct drm_crtc *crtc); void gen2_irq_reset(struct intel_uncore *uncore); void gen3_irq_reset(struct intel_uncore *uncore, i915_reg_t imr,
Add enable/disable flip done functions and the flip done handler function which handles the flip done interrupt. Enable the flip done interrupt in IER. Enable flip done function is called before writing the surface address register as the write to this register triggers the flip done interrupt Flip done handler is used to send the page flip event as soon as the surface address is written as per the requirement of async flips. The interrupt is disabled after the event is sent. v2: -Change function name from icl_* to skl_* (Paulo) -Move flip handler to this patch (Paulo) -Remove vblank_put() (Paulo) -Enable flip done interrupt for gen9+ only (Paulo) -Enable flip done interrupt in power_well_post_enable hook (Paulo) -Removed the event check in flip done handler to handle async flips without pageflip events. Signed-off-by: Karthik B S <karthik.b.s@intel.com> --- drivers/gpu/drm/i915/display/intel_display.c | 7 +++ drivers/gpu/drm/i915/i915_irq.c | 51 ++++++++++++++++++++ drivers/gpu/drm/i915/i915_irq.h | 2 + 3 files changed, 60 insertions(+)