From patchwork Mon Jun 22 13:00:20 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Shankar, Uma" X-Patchwork-Id: 11617601 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id F4218913 for ; Mon, 22 Jun 2020 12:30:34 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id DCF8A206BE for ; Mon, 22 Jun 2020 12:30:34 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org DCF8A206BE Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 988C86E59D; Mon, 22 Jun 2020 12:30:32 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by gabe.freedesktop.org (Postfix) with ESMTPS id 8273A6E566 for ; Mon, 22 Jun 2020 12:30:28 +0000 (UTC) IronPort-SDR: i/4IqBZkUutXFvCyCkodW6n7IJZ0Yrzq7foR5pdwOeJBJE5NFez3RU2RRPVLY5YVBfZp9lN5c9 lhlPqmegcQuw== X-IronPort-AV: E=McAfee;i="6000,8403,9659"; a="208946821" X-IronPort-AV: E=Sophos;i="5.75,266,1589266800"; d="scan'208";a="208946821" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Jun 2020 05:30:10 -0700 IronPort-SDR: 98Lfv4O/32w+367TrSA23VREZXgxrOkDnV/8wG7e7tzgv7dltL4+uCDNdxXsQX6Vk1Lmvn8lKF tqqusfTx6bTQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.75,266,1589266800"; d="scan'208";a="292832536" Received: from unknown (HELO linuxpresi1-desktop.iind.intel.com) ([10.223.74.152]) by orsmga002.jf.intel.com with ESMTP; 22 Jun 2020 05:30:08 -0700 From: Uma Shankar To: intel-gfx@lists.freedesktop.org Date: Mon, 22 Jun 2020 18:30:20 +0530 Message-Id: <20200622130029.28667-2-uma.shankar@intel.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20200622130029.28667-1-uma.shankar@intel.com> References: <20200622130029.28667-1-uma.shankar@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [v4 01/10] drm/i915/display: Add HDR Capability detection for LSPCON X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jani.nikula@intel.com Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" LSPCON firmware exposes HDR capability through LPCON_CAPABILITIES DPCD register. LSPCON implementations capable of supporting HDR set HDR_CAPABILITY bit in LSPCON_CAPABILITIES to 1. This patch reads the same, detects the HDR capability and adds this to intel_lspcon struct. v2: Addressed Jani Nikula's review comment and fixed the HDR capability detection logic Signed-off-by: Uma Shankar --- .../drm/i915/display/intel_display_types.h | 1 + drivers/gpu/drm/i915/display/intel_lspcon.c | 30 +++++++++++++++++++ 2 files changed, 31 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 4b0aaa3081c9..ca99a05f52da 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1386,6 +1386,7 @@ struct intel_lspcon { bool active; enum drm_lspcon_mode mode; enum lspcon_vendor vendor; + bool hdr_supported; }; struct intel_digital_port { diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c b/drivers/gpu/drm/i915/display/intel_lspcon.c index 6ff7b226f0a1..70bd564cae46 100644 --- a/drivers/gpu/drm/i915/display/intel_lspcon.c +++ b/drivers/gpu/drm/i915/display/intel_lspcon.c @@ -35,6 +35,8 @@ #define LSPCON_VENDOR_PARADE_OUI 0x001CF8 #define LSPCON_VENDOR_MCA_OUI 0x0060AD +#define DPCD_MCA_LSPCON_HDR_STATUS 0x70003 + /* AUX addresses to write MCA AVI IF */ #define LSPCON_MCA_AVI_IF_WRITE_OFFSET 0x5C0 #define LSPCON_MCA_AVI_IF_CTRL 0x5DF @@ -104,6 +106,32 @@ static bool lspcon_detect_vendor(struct intel_lspcon *lspcon) return true; } +static void lspcon_detect_hdr_capability(struct intel_lspcon *lspcon) +{ + struct intel_digital_port *intel_dig_port = + container_of(lspcon, struct intel_digital_port, lspcon); + struct drm_device *dev = intel_dig_port->base.base.dev; + struct intel_dp *dp = lspcon_to_intel_dp(lspcon); + u8 hdr_caps; + int ret; + + /* Enable HDR for MCA based LSPCON devices */ + if (lspcon->vendor == LSPCON_VENDOR_MCA) + ret = drm_dp_dpcd_read(&dp->aux, DPCD_MCA_LSPCON_HDR_STATUS, + &hdr_caps, 1); + else + return; + + if (ret < 0) { + drm_dbg_kms(dev, "hdr capability detection failed\n"); + lspcon->hdr_supported = false; + return; + } else if (hdr_caps & 0x1) { + drm_dbg_kms(dev, "lspcon capable of HDR\n"); + lspcon->hdr_supported = true; + } +} + static enum drm_lspcon_mode lspcon_get_current_mode(struct intel_lspcon *lspcon) { enum drm_lspcon_mode current_mode; @@ -581,6 +609,8 @@ bool lspcon_init(struct intel_digital_port *intel_dig_port) return false; } + lspcon_detect_hdr_capability(lspcon); + connector->ycbcr_420_allowed = true; lspcon->active = true; DRM_DEBUG_KMS("Success: LSPCON init\n");