From patchwork Wed Jul 15 22:42:12 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Navare, Manasi" X-Patchwork-Id: 11666347 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D53AA138C for ; Wed, 15 Jul 2020 22:40:30 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id BE33E20658 for ; Wed, 15 Jul 2020 22:40:30 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org BE33E20658 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id DAD426EBAB; Wed, 15 Jul 2020 22:40:24 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTPS id 8AFE86EBAB for ; Wed, 15 Jul 2020 22:40:23 +0000 (UTC) IronPort-SDR: n811PU7DbgXvvXxSxtc4urfreJuNrpjaiPOrPveMplifD8p8laCMeD0kElr2ZWc76ex3pxSUBj WLdkB900nXBg== X-IronPort-AV: E=McAfee;i="6000,8403,9683"; a="167412048" X-IronPort-AV: E=Sophos;i="5.75,357,1589266800"; d="scan'208";a="167412048" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Jul 2020 15:40:22 -0700 IronPort-SDR: j36c69zPViFbUbnWLYAGi6AOFlSIXk2D8YF8jXhwz7ZmFe7hYxhanUi2mTxkELOKXFlJn2Grz/ nZCc2IpzCOwQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.75,357,1589266800"; d="scan'208";a="316850641" Received: from labuser-z97x-ud5h.jf.intel.com ([10.165.21.211]) by orsmga008.jf.intel.com with ESMTP; 15 Jul 2020 15:40:22 -0700 From: Manasi Navare To: intel-gfx@lists.freedesktop.org Date: Wed, 15 Jul 2020 15:42:12 -0700 Message-Id: <20200715224222.7557-1-manasi.d.navare@intel.com> X-Mailer: git-send-email 2.19.1 MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v6 01/11] HAX to make DSC work on the icelake test system X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Maarten Lankhorst DSC is available on the display emulator, but not set in DPCD. Override the entries to allow bigjoiner testing. Signed-off-by: Maarten Lankhorst --- drivers/gpu/drm/drm_dp_helper.c | 4 ++-- include/drm/drm_dp_helper.h | 1 + 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c index a3c82e726057..d3aa9b696e31 100644 --- a/drivers/gpu/drm/drm_dp_helper.c +++ b/drivers/gpu/drm/drm_dp_helper.c @@ -1434,7 +1434,7 @@ u8 drm_dp_dsc_sink_max_slice_count(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE], if (slice_cap1 & DP_DSC_4_PER_DP_DSC_SINK) return 4; if (slice_cap1 & DP_DSC_2_PER_DP_DSC_SINK) - return 2; + return 4; if (slice_cap1 & DP_DSC_1_PER_DP_DSC_SINK) return 1; } else { @@ -1458,7 +1458,7 @@ u8 drm_dp_dsc_sink_max_slice_count(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE], if (slice_cap1 & DP_DSC_4_PER_DP_DSC_SINK) return 4; if (slice_cap1 & DP_DSC_2_PER_DP_DSC_SINK) - return 2; + return 4; if (slice_cap1 & DP_DSC_1_PER_DP_DSC_SINK) return 1; } diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h index e47dc22ebf50..2cce09a37e95 100644 --- a/include/drm/drm_dp_helper.h +++ b/include/drm/drm_dp_helper.h @@ -1416,6 +1416,7 @@ int drm_dp_dsc_sink_supported_input_bpcs(const u8 dsc_dpc[DP_DSC_RECEIVER_CAP_SI static inline bool drm_dp_sink_supports_dsc(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]) { + return dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT]; return dsc_dpcd[DP_DSC_SUPPORT - DP_DSC_SUPPORT] & DP_DSC_DECOMPRESSION_IS_SUPPORTED; }