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[1/2] drm/i915/dp: HAX Try the bspec value for CLKTOP2_CORECLKCTL

Message ID 20200716232900.28414-1-manasi.d.navare@intel.com (mailing list archive)
State New, archived
Headers show
Series [1/2] drm/i915/dp: HAX Try the bspec value for CLKTOP2_CORECLKCTL | expand

Commit Message

Navare, Manasi July 16, 2020, 11:28 p.m. UTC 
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 4 ++++
 drivers/gpu/drm/i915/i915_reg.h               | 1 +
 2 files changed, 5 insertions(+)
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index aeb6ee395cce..229c942aa7d7 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -3142,6 +3142,10 @@  static bool icl_mg_pll_find_divisors(int clock_khz, bool is_dp, bool use_ssc,
 			state->mg_clktop2_coreclkctl1 =
 				MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO(a_divratio);
 
+			if (is_dkl && !(a_divratio & 1))
+				state->mg_clktop2_coreclkctl1 |=
+					MG_CLKTOP2_CORECLKCTL1_A_DIVRETIMER_EN;
+
 			state->mg_clktop2_hsclkctl =
 				MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL(tlinedrv) |
 				MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL(inputsel) |
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b9607ac3620d..c11aa7c4d708 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -10323,6 +10323,7 @@  enum skl_power_gate {
 #define   MG_CLKTOP2_CORECLKCTL1_B_DIVRATIO_MASK	(0xff << 16)
 #define   MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO(x)		((x) << 8)
 #define   MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO_MASK	(0xff << 8)
+#define   MG_CLKTOP2_CORECLKCTL1_A_DIVRETIMER_EN	(1 << 1)
 #define MG_CLKTOP2_CORECLKCTL1(tc_port) _MMIO_PORT((tc_port), \
 						   _MG_CLKTOP2_CORECLKCTL1_PORT1, \
 						   _MG_CLKTOP2_CORECLKCTL1_PORT2)