| Message ID | 20200718000437.69033-2-umesh.nerlige.ramappa@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Allow privileged user to map the OA buffer | expand |
On 18/07/2020 03:04, Umesh Nerlige Ramappa wrote: > From: Piotr Maciejewski <piotr.maciejewski@intel.com> > > A clock gating switch can control if the performance monitoring and > observation logic is enaled or not. Ensure that we enable the clocks. > > v2: Separate code from other patches (Lionel) > > Fixes: 00a7f0d7155c ("drm/i915/tgl: Add perf support on TGL") > Signed-off-by: Piotr Maciejewski <piotr.maciejewski@intel.com> > Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com> > --- > drivers/gpu/drm/i915/i915_perf.c | 8 ++++++++ > drivers/gpu/drm/i915/i915_reg.h | 2 ++ > 2 files changed, 10 insertions(+) > > diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c > index c6f6370283cf..88610d52f30b 100644 > --- a/drivers/gpu/drm/i915/i915_perf.c > +++ b/drivers/gpu/drm/i915/i915_perf.c > @@ -2493,6 +2493,14 @@ gen12_enable_metric_set(struct i915_perf_stream *stream, > (period_exponent << GEN12_OAG_OAGLBCTXCTRL_TIMER_PERIOD_SHIFT)) > : 0); > > + /* > + * Initialize Super Queue Internal Cnt Register > + * Set PMON Enable in order to collect valid metrics. > + */ > + intel_uncore_write(uncore, GEN12_SQCNT1, > + intel_uncore_read(uncore, GEN12_SQCNT1) | > + GEN12_SQCNT1_PMON_ENABLE); Thanks for splitting this. We just need to also disable this when i915-perf is disabled, documentation says it saved power when turned off. -Lionel > + > /* > * Update all contexts prior writing the mux configurations as we need > * to make sure all slices/subslices are ON before writing to NOA > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index b9607ac3620d..1638f1282541 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -696,6 +696,8 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) > #define OABUFFER_SIZE_16M (7 << 3) > > #define GEN12_OA_TLB_INV_CR _MMIO(0xceec) > +#define GEN12_SQCNT1 _MMIO(0x8718) > +#define GEN12_SQCNT1_PMON_ENABLE (1 << 30) > > /* Gen12 OAR unit */ > #define GEN12_OAR_OACONTROL _MMIO(0x2960)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c index c6f6370283cf..88610d52f30b 100644 --- a/drivers/gpu/drm/i915/i915_perf.c +++ b/drivers/gpu/drm/i915/i915_perf.c @@ -2493,6 +2493,14 @@ gen12_enable_metric_set(struct i915_perf_stream *stream, (period_exponent << GEN12_OAG_OAGLBCTXCTRL_TIMER_PERIOD_SHIFT)) : 0); + /* + * Initialize Super Queue Internal Cnt Register + * Set PMON Enable in order to collect valid metrics. + */ + intel_uncore_write(uncore, GEN12_SQCNT1, + intel_uncore_read(uncore, GEN12_SQCNT1) | + GEN12_SQCNT1_PMON_ENABLE); + /* * Update all contexts prior writing the mux configurations as we need * to make sure all slices/subslices are ON before writing to NOA diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index b9607ac3620d..1638f1282541 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -696,6 +696,8 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) #define OABUFFER_SIZE_16M (7 << 3) #define GEN12_OA_TLB_INV_CR _MMIO(0xceec) +#define GEN12_SQCNT1 _MMIO(0x8718) +#define GEN12_SQCNT1_PMON_ENABLE (1 << 30) /* Gen12 OAR unit */ #define GEN12_OAR_OACONTROL _MMIO(0x2960)